User’s Manual
Preliminary PPC440x5 CPU Core
ppc440x5IX.fm.
September 12, 2002 Page 585 of 583
rfi,167,397
rfmci,398
rlwimi,399
rlwimi.,399
rlwinm,400
rlwinm.,400
rlwnm,403
rlwnm.,403
rotlw,403
rotlw.,403
rotlwi,401
rotlwi.,401
rotrwi,401
rotrwi.,401
RSTCFG,79,509
S
Save/Restore Register 0,167
Save/Restore Register 1,167
sc,404
secondary opcodes,559
self-modifying code,106
shadow TLB arrays,151
slw,405
slw.,405
slwi,401
slwi.,401
software
interrupt ordering requirements,199
Special Purpose Registers. See also SPRs
speculative fetching,81
speculative prefetch mechamism,105
SPRG0 SPRG7,75
SPRG0-SPRG3,75
SPRG0-SPRG7,510
SPRs
defined,52
sraw,406
sraw.,406
srawi,407
srawi.,407
SRR0,167,511
SRR1,167,512
srw,408
srw.,408
srwi,402
srwi.,402
stb,409
stbu,410
stbux,411
stbx,412
sth,413
sthbrx,414
sthu,415
sthux,416
sthx,417
stmw,418
storage access ordering,124
storage attributes
caching inhibited,145
endian,146
guarded,146
Memory Coherence Required,146
supported combinations,147
user-definable (U0–U3),147
write-through required,145
storage control instruction summary,62
storage control instructions
cache management,62
TLB management,62
storage operands,39
storage synchronization,84
storage synchronization instruction summary,63
store gathering,119
store miss
allocation of data cache line,119
store operations,119
structure mapping
big endian,44
little endian,44
stswi,418
stw,422
stwbrx,423
stwcx.,424
stwu,426
stwux,427
stwx,428
sub,429
sub.,429
subc,430
subc.,430
subco,430
subco.,430
subf,429
subf.,429
subfc,430
subfc.,430
subfco,430
subfco.,430
subfe,431
subfe.,431
subfeo,431
subfeo.,431
subfic,432
subfme,433
subfme.,433
subfmeo,433
subfmeo.,433
subfo,429
subfo.,429