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Intel manual PD672X/30/32/33 - ZV Port Implementation, Application Note

Models: PD672X/30/32/33

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PD672X/30/32/33 — ZV Port Implementation

Application Note

May 2001

As of May 2001, this document replaces the Basis Communications Corp. document AN-PD10.

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Intel manual PD672X/30/32/33 - ZV Port Implementation, Application Note

Contents

Application Note PD672X/30/32/33 - ZV Port ImplementationApplication Note Figures ContentsTables PD672X/30/32/33 - ZV Port ImplementationApplication Note PD672X/30/32/33 - ZV Port ImplementationPD672X/30/32/33 - ZV Port Implementation 1.0IntroductionApplication Note 3.0Zoomed Video ZV 2.0Overview4.0A Typical ZV Port Implementation PD672X/30/32/33 - ZV Port ImplementationFigure 1. Typical ZV Port Implementation PD672X/30/32/33 - ZV Port ImplementationApplication Note PD672X/30/32/33 - ZV Port Implementation A buffer circuit placed between the PC Card bus and the VGA video port reduces the trace length to lower the loading effect. The ZV Port standard requires that the length of the trace between the PC Card connector and the buffer if used must be less than two inches. Buffers are also needed to support ZV Port PC Cards in either socketApplication Note PD672X/30/32/33 - ZV Port Implementation GD7XXXApplication Note GD7XXX 6.0Buffer Implementation for Audio DACPD672X/30/32/33 - ZV Port Implementation Application NoteGD7XXX 7.0ZV Port Implementation for Socket A and BPD672X/30/32/33 - ZV Port Implementation Application NoteApplication Note PD672X/30/32/33 - ZV Port ImplementationPC Card Application Note PD672X/30/32/33 - ZV Port ImplementationApplication Note PD672X/30/32/33 - ZV Port ImplementationMCLK PD672X/30/32/33 - ZV Port Implementation 8.0Layout GuidelinesApplication Note