Intel® RAID Controller SASMF8I Hardware User’s Guide 3
Auto-resume of initialization or rebuild on reboot (the auto rebuild feature must be
enabled before virtual disk creation).
Smart initialization automatically checks consistency of virtual disks if there are five
or more disks in a RAID 5 array, which optimizes performance by enabling read-
modify-write mode. RAID 5 arrays of only three or overdrives use peer read mode.
Smart Technology predicts failures of drives and electronic components.
Commands are retried at least four times.
Firmware provides best effort to recognize an error and recover from it if possible.
Failures are logged from controller and drive firmware, SMART monitor, and SAF-
TE controller.
Failures are logged in Intel® RAID Web Console 2 or CIM, and can be viewed from
LEDs.
Multiple cache options provide choice of speed and redundancy:
Disk Write Cache: The data written / (done) signal is returned when data is
written to the drive or only to the drive’s cache.
On (default): Write back mode enabled. Faster, because it does not wait for
the disk, but data will be lost if power is lost.
Off: Write-through mode enabled. Slower, but ensures data is on the disk.
Read Ahead: Predicts the next read will be sequential and buffers this data into
the drive’s cache.
On: Read Ahead mode enabled. Faster in data sequential read mode but
slower in data random read mode.
Off: Non-Read Ahead mode enabled. Always reads from the drive after
determining the exact location of each read.
Redundancy through:
Configuration stored in non-volatile RAM and on the drives (COD).
Hot-swap support.
SAS and SATA Features
Provides eight independent PHYs, each supporting 3.0 Gbps and 1.5 Gbps SAS and
SATA data transfers.
Scalable interface that supports up to eight direct-attached SAS/SATA devices or
eight logical devices.
Transfers data using SCSI information units.
Supports SSP to enable communication with other SAS devices.
Supports SMP to communicate topology management information.
Supports single PHY or wide ports consisting of two, three, or four PHYs within a
single quad port.