4.6Advanced Chipset Setup
This section allows you to configure the system based on the specific features of the installed chipset. This chipset manages bus speeds and the access to the system memory resources, such as DRAM and the external cache. It also coordinates the communications between the conventional ISA and PCI buses. It must be stated that these items should never be altered. The default settings have been chosen because they provide the best operating conditions for your system. You might consider and make any changes only if you discover that the data has been lost while using your system.
AMIBIOS SETUP – ADVANCED CHIPSET SETUP(C)2001 American Megatrends, Inc. All Rights Reserved
******** DRAM Timing ******** |
| Available Options: | |
Configure SDRAM Timing by SPD | Enabled | ` Disabled |
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SDRAM Frequency | Auto | Enabled |
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SDRAM CAS# Latency | 2.5 |
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SDRAM Bank Interleave | Disabled |
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SDRAM Command Rate | 2T |
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Memory Hole | Disabled |
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Auto Prechrage for TLB/WB | Disabled |
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Write Recovery time | 2T |
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AGP Mode | 4x |
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AGP Read Synchronization | Disabled |
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AGP Fast Write | Disabled |
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AGP Comp. Driving | Auto |
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Manual AGP Comp. Driving | CB |
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AGP Aperture Size | 64MB |
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AGP Master 1 W/S Write | Disabled |
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AGP Master 1 W/S Read | Disabled |
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Search for MDA Resources | Yes |
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PCI Delay Transaction | Enabled |
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USB Controller | 4 USB Ports |
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USB Device Legacy Support | All Device |
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Disabled | ESC: Exit | : Sel | |
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| PgUp/PgDn: Modify | |
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| F2/F3: Color |
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