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Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes LGE Internal Use Only

LG1154

TDSQ-
G651D
[RESET] 2 AG6[GPIO10]
AH34 [SCL5]
AH33 [SDA5]
[SLC] 3
[SDA] 4
[+3.3V_TUNER] 5
[+.1.8V_TUNER] 7
[CVBS] 8
[ERROR] 16
[SYNC] 17
[VALID] 18
[MCLK] 19
AL37[TP_DVB_ERR]
AL36 [TP_DVB_SOP]
AL35 [TP_DVB_VAL]
AM36 [TP_DVB_CLK]
[D0-7] 20-27
[+1.23V_S2_DEMOD] 30
[S2_RESET] 31 AM18 [ADIN7_SRV]
[+3.3V_S2_DEMOD] 32
LNB
IC6900
A8303SESTR-TB
10 [TONECTRL]
2 [LNB]
7 [SCL]
8 [SDA]
[S2_F22_OUTPUT] 33
[LNB] 36
[S2_SCL] 34
[S2_SDA] 35
AP6 [SCL3]
AR6 [SDA3]
V15[CVBS_IN1]
H18[AAD_ADC_SIF]
/TU_RESET1
IC2_SCL6
IC2_SDA6
FE_DEMOD1_TS_ERROR
FE_DEMOD1_TS_SYNC
FE_DEMOD1_TS_VAL
FE_DEMOD1_TS_CLK
FE_DEMOD1_TS_DATA [0-7]
+1.23V_D_Demod
/S2_RESET
LNB_TX
I2C_SCL4
I2C_SDA4
22 Ω
LNB_OUT
+3.3V_NORMAL
3.3K Ω
+1.8_TU
+3.3V_TU
+3.3V_D_Demod
CVBS
TUNER_SIF
33 Ω 33Ω
33 Ω

CI Slot

100 Ω CI_TS_DATA[0-7]
/PCM_WE
/PCM_OE
/PCM_IRQA
/PCM_REG
PCM_INPACK
/PCM_WAIT
PCM_RST
CI_DATA[0-7] CI_A_DATA[0-7]
CI_ADDR[0-14] CI_A_ADDR[0-14]
/PCM_IORD
/PCM_IOWR
/PCM_CE2
/PCM_CE1
CI_VS1
/CI_CD1
/CI_CD2
CI 5V
Power detect
PCM_5V_CTL +5V_CI_ON
CI_TS_SYNC
CI_TS_VAL
CI_TS_CLK
[TP_DVB_DATA0-7]
TPO_DATA[0-7]
TPI_DATA[0-7]
CI_DET1
D32[CAM_CD1_N]
CI_DET2
E32[CAM_CD2_N]
VS1 G32[CAM_VS1_N]
F33[CAM_CE1_N] CARD_EN1
CARD_EN2
10K Ω
H37[EB_BE_N0]
H36[EB_BE_N1]
IOWR
IORD
[EB_ADDR0-14]
[EB_DATA0-7]
ADDR[0-14]
DATA[0-7]
G34[CAM_RESET]
E33[CAM_WAIT]
D34[CAM_REG]
F32[CAM_IREQ]
J36[EB_OE]
H35[EB_WE]
A28[TPI_CLK]
B28[TPI_VAL]
B29[TPI_SOP]
TS_OUT_CLK
TS_OUT_VAL
TS_OUT_SYNC
CI_RESET
CI_WAIT
INPACK
REG
/IRQA
O_EN
WR_EN
VCC
H32
[CAM_VCCEN_N]
+5V_CI_ON +5V_NORMAL
10K Ω
CI_IN_TS_DATA[0-7]
100Ω
[SIF] 6
F34[CAM_CE2_N]
D33[CAM_INPACK]
4. Tuner/CI Block Diagram