THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
R9309
100
C9308
0.1uF
16VOPT
R9308
100
SPI_DO
SOC_TXA3N TXA3P
R9319 33
+3.3V_IO
TXB4N
TXB2P
SOC_TXA2P
R9311
100
R9304
100
R9334
4.7K
TMS
R9339 100 OPT
R9329
1M
C9304
0.1uF
16VOPT
SOC_TXB0P TXB0N
R9336
100K
1/16W
SW9300
JTP-1127WEM
DEBUG
12
4 3
I2C_SDA2
R9302
100
R9337
33
SOC_TXB3N
+3.3V_XTAL_AVDD
C9354
0.1uF
16VOPT
TMODE0
+2.5V_LVDS_TX
TXA4P
R9331 0
DEBUG
SOC_TXA1P
P9300
12507WR-10L
DEBUG
1
2
3
4
5
6
7
8
9
10
11
R9312 33
+2.5V_LG1132
C9366
0.1uF
16VOPT
XTAL_OUT
R9328
10K
OPT
+3.3V_NORMAL
R9323 10K
TXB1P
I2C_SDA2
TMODE0
TXA0P
TMS
+2.5V_LVDS_RX
SOC_TXB2P
TXA4N
R9310
100
SPI_SCLK
R9324 10K
OPT
C9324
0.1uF
16V
SOC_TXA2N
SOC_TXA1N
R9338 100 OPT
TXB3N
TRST_N
+3.3V_NORMAL
TCK TCK
+3.3V_IO
SPI_SCLK
SOC_TXBCLKN
XTAL_IN
SMODE
TXB4P
SPI_DI
SPI_DO
TDO
SOC_TXB1P
TDO
R9307
100
SOC_TXA0P
C9364
0.1uF
16VOPT
+3.3V_XTAL_AVDD
C9348
0.1uF
16VOPT
+2.5V_AVDD
XTAL_OUT
R9303
100
SOC_TXB4P
TMODE1
+1.0V_PLL_VDD
SPI_SCLK
3D_DEPTH_RESET
+1.0VDC
XTAL_IN
FLASH_WP
SOC_TXBCLKP
TMODE3
I2C_SCL2
R9313 33
+3.3V_NORMAL
+2.5V_LVDS_RX
R9321 10K
NON_72INCH_LVDS_AB
R9340 100 OPT
SOC_TXA4P
R9330 0
OPT
+3.3V_IO
R9325 10K
TXA1N
TXA1P
R9335
10K
OPT
+1.0VDC
R9341 100 OPT
R9326 10K
OPT
SOC_TXB2N
SPI_DO
SPI_CS
C9365
0.1uF
TXB0P
C9323
0.1uF
16VOPT
TMODE3
R9301
100
SOC_TXA3P
TXB2N
SOC_TXA4N
TRST_N
TXACLKP
C9314
0.1uF
16V
R9317 33
+2.5V_LVDS_TX
SOC_TXB1N
R9316 33
C9327
0.1uF
16VOPT
R9315 33
TXB3P
+2.5V_AVDD
FLASH_WP
R9318 33
TXBCLKP
+3.3V_NORMAL
+2.5V_LVDS_TX
TMODE0
SOC_TXB4N
R9305
100
R9343
3.3K
+2.5V_LG1132
C9300
0.1uF
16VOPT
TDI
SOC_TXA0N
TMODE1
TMODE2
C9328
0.1uF
16V
TXACLKN
TXA0N
C9359
0.1uF
16V
SPI_DI
R9314 33
+2.5V_LVDS_RX
3D_DEPTH_RESET
R9342 100
+3.3V_NORMAL
R9320 10K
OPT
C9322
0.1uF
16VOPT
TXB1N
SOC_TXB0N
C9326
0.1uF
16VOPT
TXA2N
+2.5V_LG1132
SPI_CS
R9322 10K
OPT
I2C_SCL2
SOC_TXACLKP
3D_DEPTH_RESET
SOC_TXACLKN
+1.0VDC
+1.0VDC
C9321
0.1uF
16VOPT
R9327 10K
R9306
100
C9363
0.1uF
16V
TXA2P
SPI_DI SMODE
SPI_CS
TDI
TMODE2
+3.3V_XTAL_AVDD
+3.3V_IO
SOC_TXB3P
+1.0V_PLL_VDD
TXBCLKN
R9300
100
TXA3N
C9330
0.1uF
16V
+2.5V_AVDD
I2C_SCL2
I2C_SDA2
I2C_SCL1
I2C_SDA1
R9344
0
OPT
R9345
0
OPT
P9301
12507WS-04L
DEBUG
1
2
3
4
5
+3.3V_NORMAL

IC9301

W25X40BVSSIG

LG1132_FLASH

3
WP
2
DO[IO1]
4
GND
1
CS
5DI[IO0]
6CLK
7HOLD
8VCC
C9315
4.7uF
10V
C9318
4.7uF
10V
C9316
4.7uF
10V
C9319
4.7uF
10V
C9317
4.7uF
10V
C9320
4.7uF
10V
C9357
4.7uF
10V
C9352
4.7uF
10V
C9310
4.7uF
10V
C9307
4.7uF
10V
C9303
4.7uF
10V
C9301
4.7uF
10V
C9353
4.7uF
10V
C9361
4.7uF
10V
C9336
4.7uF
+1.0V_PLL_VDD
+1.0VDC
R9333 0
OPT
R9332 0
OPT
MDS62110213
M9301 ALBLOCK
MDS62110213
M9302 ALBLOCK
MDS62110213
M9300 ALBLOCK
MDS62110213
M9303 ALBLOCK
TXCCLKN
TXDCLKN
TXC4N
TXC1N
TXC4P
TXD0P
TXC3N
TXC2P
TXC0N
TXD3P
TXDCLKP
TXD3N
TXD2N
TXC3P
TXC1P
TXC0P
TXD4N
TXCCLKP
TXC2N
TXD1P
TXD0N
TXD4P
TXD1N
TXD2P
TXD0P
TXD0N
TXC3N
TXACLKN
TXD3N
TXD4P
TXDCLKNTXBCLKN
TXD1P
TXD3P
TXCCLKP
TXA4N
TXA1N
TXA4P
TXB0P
TXA3N
TXC0N
TXA2P
TXA0N
TXB3P
TXD1N
TXBCLKP
TXB3N
TXD4N
TXB2N
TXA3P
TXDCLKP
TXA1P
TXC4N
TXD2P
TXA0P
TXB4N
TXACLKP TXCCLKN
TXC3P
TXD2N
TXC2P
TXC2N
TXC1P
TXA2N
TXB1P
TXB0N
TXC1N
TXB4P
TXC4P
TXC0P
TXB1N
TXB2P
L9300
BLM18SG121TN1D
L9302
BLM18SG121TN1D
L9303
BLM18SG121TN1D
L9305
BLM18SG121TN1D
L9304
BLM18SG121TN1D
L9309
BLM18SG121TN1D
C9360
10uF
10V
C9312
10uF
10V
C9311
10uF
10V
C9356
10uF
10V

IC9300

LG1132

RXA0P
AB17
RXA0N
AA17
RXA1P
Y16
RXA1N
Y17
RXA2P
AA16
RXA2N
AB16
RXACLKP
AB15
RXACLKN
AA15
RXA3P
Y14
RXA3N
Y15
RXA4P
AA14
RXA4N
AB14
RXB0P
AB13
RXB0N
AA13
RXB1P
Y12
RXB1N
Y13
RXB2P
AA12
RXB2N
AB12
RXBCLKP
AB11
RXBCLKN
AA11
RXB3P
Y10
RXB3N
Y11
RXB4P
AA10
RXB4N
AB10
RXC0P
AB9
RXC0N
AA9
RXC1P
Y8
RXC1N
Y9
RXC2P
AA8
RXC2N
AB8
RXCCLKP
AB7
RXCCLKN
AA7
RXC3P
Y6
RXC3N
Y7
RXC4P
AA6
RXC4N
AB6
RXD0P
AB5
RXD0N
AA5
RXD1P
Y4
RXD1N
Y5
RXD2P
AA4
RXD2N
AB4
RXDCLKP
AB3
RXDCLKN
AA3
RXD3P
Y2
RXD3N
Y3
RXD4P
AA2
RXD4N
AB2
UART_RXD
D3
UART_TXD
D2
SPI_SCLK
C2
SPI_CS
C1
SPI_DI
B1
SPI_DO
B2
SDA_M
E2
SCL_M
E1
SDA_S
D1
SCL_S
E3
SMODE
F2
TMODE0
F1
TMODE1
G3
TMODE2
G2
TMODE3
G1
TRST_N
H1
TDO
H3
TDI
H2
TCK
J3
TMS
J2
PORES_N
F3
XTALO
AB21
XTALI
AA21
TXA0P A10
TXA0N B10
TXA1P C9
TXA1N C10
TXA2P B9
TXA2N A9
TXACLKP A8
TXACLKN B8
TXA3P C7
TXA3N C8
TXA4P B7
TXA4N A7
TXB0P A6
TXB0N B6
TXB1P C5
TXB1N C6
TXB2P B5
TXB2N A5
TXBCLKP A4
TXBCLKN B4
TXB3P C3
TXB3N C4
TXB4P B3
TXB4N A3
TXC0P A18
TXC0N B18
TXC1P C17
TXC1N C18
TXC2P B17
TXC2N A17
TXCCLKP A16
TXCCLKN B16
TXC3P C15
TXC3N C16
TXC4P B15
TXC4N A15
TXD0P A14
TXD0N B14
TXD1P C13
TXD1N C14
TXD2P B13
TXD2N A13
TXDCLKP A12
TXDCLKN B12
TXD3P C11
TXD3N C12
TXD4P B11
TXD4N A11
GPIO[0] Y1
GPIO[1] W3
GPIO[2] W2
GPIO[3] W1
GPIO[4] V3
GPIO[5] V2
GPIO[6] V1
GPIO[7] U3
GPIO[8] U2
GPIO[9] U1
GPIO[10] T3
GPIO[11] T2
GPIO[12] T1
GPIO[13] R3
GPIO[14] R2
GPIO[15] R1
GPIO[16] P3
GPIO[17] P2
GPIO[18] P1
GPIO[19] N3
GPIO[20] N2
GPIO[21] N1
GPIO[22] M3
GPIO[23] M2
GPIO[24] M1
GPIO[25] L1
GPIO[26] L2
GPIO[27] L3
GPIO[28] K1
GPIO[29] K2
GPIO[30] K3
GPIO[31] J1

IC9300

LG1132

VDD_1
H8
VDD_2
H9
VDD_3
H14
VDD_4
H15
VDD_5
J8
VDD_6
J15
VDD_7
K8
VDD_8
K15
VDD_9
L8
VDD_10
L15
VDD_11
M8
VDD_12
M15
VDD_13
N8
VDD_14
N15
VDD_15
P8
VDD_16
P15
VDD_17
R8
VDD_18
R9
VDD_19
R10
VDD_20
R11
VDD_21
R12
VDD_22
R13
VDD_23
R14
VDD_24
R15
VDD33_1
F4
VDD33_2
G4
VDD33_3
H4
VDD33_4
J4
VDD33_5
K4
VDD33_6
L4
VDD33_7
M4
VDD33_8
N4
VDD33_9
P4
VDD33_10
R4
VDD33_11
T4
VDD33_12
U4
LVRX_VDD25_1
W7
LVRX_VDD25_2
W8
LVRX_VDD25_3
W9
LVRX_VDD25_4
W10
LVRX_VDD25_5
W11
LVRX_VDD25_6
W12
LVRX_VDD25_7
W13
LVRX_VDD25_8
W14
LVTX_VDD10_1
H10
LVTX_VDD10_2
H11
LVTX_VDD10_3
H12
LVTX_VDD10_4
H13
LVTX_VDD25_1
D7
LVTX_VDD25_2
D8
LVTX_VDD25_3
D9
LVTX_VDD25_4
D10
LVTX_VDD25_5
D11
LVTX_VDD25_6
D12
LVTX_VDD25_7
D13
LVTX_VDD25_8
D14
LVTX_VDD25_9
D15
LVTX_VDD25_10
D16
DISP_VDD
Y21
DR3P_VDD
Y22
SSP_VDD
AA22
XTAL_VDD
Y20
DISP_AVDD
AA19
DR3P_AVDD
AA20
SSP_AVDD
AB20
XTAL_AVDD
AB19
VSS_1
A2
VSS_2
A19
VSS_3
B19
VSS_4
C19
VSS_5
D4
VSS_6
D5
VSS_7
D6
VSS_8
D17
VSS_9
D18
VSS_10
D19
VSS_11
E4
VSS_12
E5
VSS_13
E6
VSS_14
E7
VSS_15
E8
VSS_16
E9
VSS_17
E10
VSS_18
E11
VSS_19
E12
VSS_20
E13
VSS_21
E14
VSS_22
E15
VSS_23
E16
VSS_24 E17
VSS_25 E18
VSS_26 F5
VSS_27 F18
VSS_28 G5
VSS_29 G18
VSS_30 H5
VSS_31 H18
VSS_32 J5
VSS_33 J9
VSS_34 J10
VSS_35 J11
VSS_36 J12
VSS_37 J13
VSS_38 J14
VSS_39 J18
VSS_40 K5
VSS_41 K9
VSS_42 K10
VSS_43 K11
VSS_44 K12
VSS_45 K13
VSS_46 K14
VSS_47 K18
VSS_48 L5
VSS_49 L9
VSS_50 L10
VSS_51 L11
VSS_52 L12
VSS_53 L13
VSS_54 L14
VSS_55 L18
VSS_56 M5
VSS_57 M9
VSS_58 M10
VSS_59 M11
VSS_60 M12
VSS_61 M13
VSS_62 M14
VSS_63 M18
VSS_64 N5
VSS_65 N9
VSS_66 N10
VSS_67 N11
VSS_68 N12
VSS_69 N13
VSS_70 N14
VSS_71 N18
VSS_72 P5
VSS_73 P9
VSS_74 P10
VSS_75 P11
VSS_76 P12
VSS_77 P13
VSS_78 P14
VSS_79 P18
VSS_80 R5
VSS_81 R18
VSS_82 T5
VSS_83 T18
VSS_84 T19
VSS_85 U5
VSS_86 U18
VSS_87 U19
VSS_88 V4
VSS_89 V5
VSS_90 V6
VSS_91 V7
VSS_92 V8
VSS_93 V9
VSS_94 V10
VSS_95 V11
VSS_96 V12
VSS_97 V13
VSS_98 V14
VSS_99 V15
VSS_100 V16
VSS_101 V17
VSS_102 V18
VSS_103 V19
VSS_104 W4
VSS_105 W5
VSS_106 W6
VSS_107 W15
VSS_108 W16
VSS_109 W17
VSS_110 W18
VSS_111 W19
VSS_112 W20
VSS_113 W21
VSS_114 W22
VSS_115 Y18
VSS_116 Y19
VSS_117 AA1
VSS_118 AA18
VSS_119 AB18
X9300
24.75MHz
4GND_2
1
X-TAL_1
2
GND_1 3X-TAL_2
C9333
30pF
50V
C9339
30pF
50V
3D DepthLG1152 B0 2011. 11. 28

XTAL(24.75MHz)

+3.3V Power Separation

+1.0VDC Decaps

LG1132 Has Internal Pull-up

SPI FLASH(4M Bit)

TEST MODE Configuration

System Configuration

+2.5V LVDS_RX Decaps

SPI/I2C For Aardvak Interface

Default Setting
All ’H’ = Normal Operation Mode

LG1132 HW RESET

Monitoring Pins for
3D-Depth Interanl status

+3.3V_IO Decaps

Default Setting(’0’)
0 : Boot From Ext. Flash(Normal Booting)
1 : Internal RAM Boot (JTAG Booting)

+2.5V LVDS_TX Decaps

+1.0V Power Separation

TMODE[3:0]
0000 => System PLL Test
0001 => LVDS Rx Isolation Test
0010 => LVDS Tx Isolation Test
0011 => LVDS Bypass Test
0100 => ALL PLL Test
1001 => DDR PLL IsolationTest
1010 => Functional Test
1011 => MBIST
1100 => Scan Test(Normal)
1101 => Scan Test (Adaptive)
1110 => Display PLL Test
1111 => Normal Operation

+1.0V_XTAL/DDR3 PLL/SS PLL/DIS PLL_VDD

+2.5V DDR PLL/SS PLL/DIS PLL AVDD Decaps

+3.3V XTAL AVDD Decaps

For Heat Sink

Copyright © 2012 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only