(EPI CH1 ±)
(EPI CH3 ±)
TX0P/N
TX2P/N
(EPI CH2 ±)
TX1P/N
EPI 50P_LEFT
(LVDS_51PIN Side)
(EPI CH4 ±)
(EPI CH6 ±)
TX3P/N
TX5P/N
(EPI CH5 ±)
TX4P/N
32/31
GMA_4/5/7/12/14/15
GMA_1/3/4/5/7/9/10/12/14/15/16/18
28/27
24/23
32/31
24/23
20/19
50~39
1~12

EPI_LOCK6_SOURCE

EPI_LOCK3
15
14
36
CLK1/2/3/4/5/6 48~43
3~8

VGH_F/R

10/9
41/42
VGH_EVEN/ODD
12/11
39/40
VCOM_P/N
VCOM
17
34

VCOM_LOOP

VCOMLFB/RFB 16
35
GIP_RST
15
36
14

37

VST

DISCHG

VGL
VGL_I
13
38

TX_LOCKN

Z_OUT
1
50

VCC18

H_VDD
V core
VDD
VCC18

H_VDD

V core
VDD
VCC18
H_VDD
V core
VDD

H13

IC100

LG1154D

LEVEL SHIFTER

IC7701

TPS65198

CTRLN
VGL_FB
SWN

PMIC

IC7700

TPS65178RSLR

VCC
CTRLP
VGH_FB
SWP
VDD
VCOM_DYN
I2C_SDA2
PMIC_RESET

I2C_SCL2

GCLK
GST
MCLK
EO
GCLK
MCLK
EO
PANEL_VCC
VGL
VGH
8. Panel Interface Block Diagram