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Basic Principles of Operation
$WHHGTThe%QPVTQNNGTBuffer Controller supports a 1.75 MB buffer. The
The Buffer Controller supports both drive and host address rollover and reloading, to allow for buffer segmentation. Drive and host addresses may be separately loaded for automated read/write functions.
The Buffer Controller operates under the direction of the µProcessor.
5GTXQThe2TQEGUUQTServo Processor in the Read Write Channel ASIC provides servo data recovery and burst demodulation to extract the actuator position information. This information is processed in the controller ASIC/microprocessor, and a control signal is output to the VCM in the Power ASIC. This controls the current in the actuator coil which controls the position of the actuator.
4GCFThe9TKVGRead/Write+PVGTHCEGinterface allows the integrated µprocessor, disk controller to communicate with the Read/Write chip.
#6#The+PVGTHCEGATA Interface%QPVTQNNGTController portion of the ASIC provides data handling, bus control, and transfer management services for the ATA interface. Configuration and control of the interface is accomplished by the µController across the MAD bus. Data
transfer operations are controlled by the Buffer Controller module.
/QVQTThe%QPVTQNNGTMotor Controller controls the spindle and voice coil motor (VCM) mechanism
on the drive.
4GCFThe9TKVGRead/Write#5+%ASIC integrates an Advanced Partial Response Maximum Likelihood (PRML) processor, a selectable code rate
The Read/Write ASIC comprises 12 main functional modules (described below):
•
•Variable Gain Amplifier (VGA)
•Butterworth Filter
•FIR Filter
Maxtor |