NetPlane Core Services

Checkpoint Service

 

 

When the Availability Manager detects failures or hardware events such as extraction/insertion requests, it triggers the Availability Director to recover affected software services. When the Availability Manager receives a hot-swap event via HPI, it checks the component’s FRU validation data to determine whether the component can be powered-on or not.

A further task includes reset management. When a reset request is received, the Availability Manager conducts a fault-domain hierarchy look-up. It then requests the Availability Director to switch-over the affected nodes and proceeds with the reset only if it received a confirmation from the Availability Director.

2.5.1.1.3Availability Node Director

The Availability Node Director (AvND) resides on each system node and its main task is to maintain the node-scoped part of the software system model described above.

The AvND coordinates local fault identification and repair of components and furthermore facilitates any wishes it receives from the Availability Director.

The AvND watches for components arriving or leaving the system and summarizes this information in a Service Unit (SU) presence state, and keeps the AvD informed about the current status and changes. The AvND is capable of disengaging, restarting and destroying any component within its scope. This may occur according to AvD instructions or as a result of an administrative action or automatically triggered by policies.

2.5.1.1.4Availability Agent

The Availability Agent (AvA) is a linkable library that exposes the SAF APIs to applications. Its task is to convey requests from the AvND or the AvD through the AvND to the application and vice versa. Details about the supported SAF APIs can be found in the NetPlane Core Services Overview User’s Guide which is part of the Avantellis documentation collection.

2.5.2Checkpoint Service

The Checkpoint Service (CPSv) implements the SAF Checkpoint Service. It provides checkpointing of data in a manner which is equivalent to hardware shared memory between nodes.

2.5.2.1Basic Functionality

The CPSv maintains a set of replicated repositories called checkpoints. Each checkpoint may have one or more replicas within the scope of a cluster. At most, one replica per checkpoint may exist on one node within a cluster.

Each checkpoint comprises one or more sections which can be dynamically created or deleted. The CPSv does not encode the data written into checkpoint sections. If checkpoints are replicated on heterogeneous nodes, for example nodes with different endian architecture, you must make sure that the data can be appropriately interpreted on all nodes.

The CPSv service supports the following two types of update options:

zAsynchronous update option

zSynchronous update option

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NetPlane Core Services Overview User’s Guide (6806800C08B)

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Motorola 6806800C08B manual Checkpoint Service, Availability Node Director, Availability Agent
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6806800C08B specifications

The Motorola 68000 microprocessor, particularly the revision marked as 68000C08B, stands out as a seminal component in the evolution of computing technology. Introduced in 1979, the 68000 architecture laid the groundwork for many advanced systems, influencing a multitude of platforms, from personal computers to game consoles.

The Motorola 68000C08B features a 16-bit data bus and a 24-bit address bus, allowing for a memory addressing capability of up to 16 MB. This architecture was pioneering for its time, enabling more extensive and complex software applications than its predecessors. The C08 revision particularly emphasized optimizing power consumption while maintaining performance, making it ideal for embedded systems and portable devices.

One of the 68000's key characteristics is its unique register set, which allows for a versatile range of operations. It consists of 8 general-purpose data registers and 8 address registers. The architecture supports both integer and floating-point operations, thanks to an integrated instruction set that facilitates complex mathematical computations, crucial for applications in graphics and gaming.

In terms of performance, the 68000 processor operates at clock speeds ranging from 8 MHz to 16 MHz, depending on the specific variant. The instruction set architecture (ISA) is known for its orthogonality, meaning that most instructions can be used interchangeably across different registers. This design simplicity allows for efficient coding and faster execution times, a significant advantage for developers.

Another remarkable feature of the 68000C08B is its capability for multitasking and improved context switching. Its advanced memory management, combined with support for virtual memory in later implementations, catered to the needs of operating systems and real-time applications, making it suitable for both consumer electronics and industrial machinery.

The Motorola 68000 family also supports a variety of peripherals, enhancing its flexibility as a microcontroller. This compatibility allowed manufacturers to create diverse product lines, from keypads and mice to modems and hard drives.

In summary, the Motorola 68000C08B microprocessor not only advanced the landscape of computer technology in the late 20th century but also helped set the stage for future innovations through its architecture, performance capabilities, and versatility in numerous applications. Its legacy continues to influence modern computing paradigms, ensuring the 68000 remains an essential chapter in the history of microprocessors.
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