20
MOTOROLA
operations that yield single-precision results , then the two register files are completely de-
coupled - thus effectively doubling the amount of registers available for the data ALU.
4.1 CHANGE TO THE PROGRAMMING MODEL (SINGLE PRECISION MODE)
To suppor t the single precision mode, bit 5 of the OMR suppor ts a new single precision
mode (SPM) bit. When OMR bit 5 is clear, the single precision mode is disabled. When
OMR bit 5 is set, the processor is in the single precision mode. The SPM bit is cleared
during reset.
4.2 SINGLE PRECISION MODE DETAILS
The processor suppor ts the following three measures to achieve the Data-ALU Register
File decoupling when it is in single precision mode:
1. Single-precision MOVE operations affect the high and middle portion of the destination
register. They DO NOT clear the low portion of the destination register.
2. Data-ALU floating-point operations that yield single-precision results affect the high
and middle portion of the destination register. They DO NOT clear the low portion of
the destination register.
3. Integer multiply operations (MPYS and MPYU) yield 64-bit results (from the condition
code’s point of view) of which only the 32 least significant bits are written into the low
portion of the destination register. The middle portion of the destination register is not
aff ected. Thus, the implication is that the largest tw o integers that can be m ultiplied in
this mode without a loss of significant digits is 16. If you are using the integer m ultiply
operation MPYS f or the m ultiplication of 16-bit numbers , you m ust sign-e xtend the up-
per 16 bits of the multiplicand and the multiplier to get a valid integer result.
These measures assure that a single-precision floating-point operation or a MOVE does
not overwrite an integer variable stored in the low portion of the destination register. Fur-
thermore these measures assure that an integer multiply does not o v erwrite a single-pre-
cision floating-point number stored in the high and middle portions of the destination
register. Thereby full decoupling is achieved.
Single Precision Mode does not affect double-precision MOVE operations, long integer
MOVE operations or the single-extended-precision floating-point operations.
31 543210
MAMBMCDECE
reserved
Single Precision Mode Bit
SPM
6