2.4.5, 2-18 Replace -11 with the following

DBP

Disable 60x bus address and data parity generation. 0 The system generates address and data parity.

1Parity generation is disabled and parity signals are driven to 0 during bus operations. When parity generation is disabled, all parity checking should also be disabled and parity signals need not be connected.

Replace the description of HID0[BTIC] (bit 26), with the following:

26 BTIC BTIC enable. Used to enable use of the 64-entry branch instruction cache.

0The BTIC contents are invalidated and the BTIC behaves as if it were empty. New entries cannot be added until the BTIC is enabled.

1 The BTIC is enabled and new entries can be added.

2.1.2.4.5, 2-18 Replace Table 2-11 with the following:

Table 2-11. PMC2 EventsÑMMCR0[26Ð31] Select Encodings

		Encoding	Description

		00 0000	Register holds current value.

		00 0001	Counts processor cycles.

		00 0010	Counts completed instructions. Does not include folded branches.

		00 0011	Counts transitions from 0 to 1 of TBL bits speciÞed through
			MMRC0[RTCSELECT]. 00 = 47, 01 = 51, 10 = 55, 11 = 63.

		00 0100	Counts instructions dispatched. 0, 1, or 2 instructions per cycle.

		00 0101	Counts L1 instruction cache misses.

		00 0110	Counts ITLB misses.

		00 0111	Counts L2 instruction misses.

		00 1000	Counts branches predicted or resolved not taken.

		00 1001	Counts MSR[PR] bit toggles.

		00 1010	Counts times reserved load operations completed.

		00 1011	Counts completed load and store instructions.

		00 1100	Counts snoops to the L1 and the L2.

		00 1101	Counts L1 cast-outs to the L2.

		00 1110	Counts completed system unit instructions.

		00 1111	Counts instruction fetch misses in the L1.

		01 0000	Counts branches allowing out-of-order execution that resolved correctly.

		All others	Reserved.

4.5.11, 4-20	Remove Table 4-10, ÒTrace ExceptionÑSRR1 Settings.Ó This
	interrupt is implemented as deÞned by the OEA. Remove the
	Table 4-10 and the introductory text.

Errata to MPC750 UserÕs Manual

MOTOROLA

MPC750 specifications

The Motorola MPC750 is a PowerPC microprocessor that was part of the PowerPC G3 family. Released in the late 1990s, it marked a significant advancement in the realm of computing performance and efficiency. Known for its robust design and versatility, the MPC750 was used in a variety of systems, from personal computers to embedded applications.

One of the standout features of the MPC750 is its implementation of the RISC (Reduced Instruction Set Computing) architecture, which enhances performance by optimizing the instruction set used in processing tasks. The processor operates with a reduced number of cycles per instruction, leading to faster execution and improved overall system efficiency. The MPC750 was built on a 0.25-micron process technology, which contributed to its compact size and lower power consumption compared to its predecessors.

The MPC750 supports clock speeds ranging from 200 MHz to 400 MHz, allowing it to cater to a range of applications where performance is paramount. This flexibility made it an appealing choice for manufacturers looking to create high-performance computing solutions. The architecture includes a high-bandwidth on-chip cache system, featuring both L1 and L2 caches. The L1 cache typically includes both data and instruction caches, while the L2 cache provides additional memory bandwidth, crucial for applications that require fast data processing.

In addition to its core processing capabilities, the MPC750 incorporates several advanced technologies, including SIMD (Single Instruction, Multiple Data) processing capabilities. This allows it to handle multiple data points with a single instruction, boosting performance in multimedia applications and data-intensive tasks. The processor also supports a variety of interfaces, making it versatile for integration into various systems.

Thermal management is another key characteristic of the MPC750. It was designed to operate efficiently at lower power levels, reducing heat generation, which is vital for maintaining system stability. This is particularly important in applications such as embedded systems where space constraints may limit cooling solutions.

Overall, the Motorola MPC750 microprocessor symbolizes a blend of performance, efficiency, and adaptability. Its combination of advanced technologies, support for RISC architecture, and features such as high-speed cache and SIMD processing made it a cornerstone of the PowerPC family and a preferred choice for developers during its time. As such, the MPC750 played a crucial role in the evolution of computing technology in the late 1990s and early 2000s.

Motorola MPC750 manual 2.4.5, 2-18 Replace -11 with the following, and the introductory text

Models: MPC750

DBP

2.1.2.4.5, 2-18 Replace Table 2-11 with the following:

Table 2-11. PMC2 EventsÑMMCR0[26Ð31] Select Encodings

Encoding

Description

Remove Table 4-10, ÒTrace ExceptionÑSRR1 Settings.Ó This

interrupt is implemented as deÞned by the OEA. Remove the

Table 4-10 and the introductory text.

MPC750 specifications