A-2 Using the SC140 Enhanced OnCE Stopwatch Timer Code A-2. EOnCE_registers.h
/* EOnCE registers */
#define EXCP_TABLE 0x7000
#define REG_BASE_ADDRESS 0x00effe00 /* EOnCE Statu s regist er */
#ifdef COMPILER_BETA_1_BUG
long EE_CTRL = REG_BASE_ADDRESS+0x18; /* EO nCE EE p ins Contr ol reg ister */
long EDCA1_CTRL = REG_BASE_ADDRESS+0x44; /* EO nCE EDCA #1 Contr ol reg ister */
long EDCA1_REFA = REG_BASE_ADDRESS+0x64; /* EO nCE EDCA #1 Refer ence V alue A * /
long EDCA1_REFB = REG_BASE_ADDRESS+0x84; /* EO nCE EDCA #1 Refer ence V alue B * /
long EDCA1_MASK = REG_BASE_ADDRESS+0xc4; /* EO nCE EDCA #1 Mask Regist er */
long ECNT_CTRL = REG_BASE_ADDRESS+0x100; /* E OnCE Cou nter Cont rol re gister * /
long ECNT_VAL = REG_BASE_ADDRESS+0x104; /* E OnCE Cou nter Valu e regi ster */
long ECNT_EXT = REG_BASE_ADDRESS+0x108; /* E OnCE Ext ension Co unter Value */
#else
#define EMCR REG_BASE_ADDRESS+0x4 /* EO nCE Moni tor and C ontrol registe r */
#define ERCV REG_BASE_ADDRESS+0x8 /* EO nCE Rece ive regis ter */
#define ETRSMT0 REG_BASE_ADDRESS+0x10 /* E OnCE Rec eive regi ster * /
#define ETRSMT1 REG_BASE_ADDRESS+0x14 /* E OnCE Rec eive regi ster * /
#define EE_CTRL REG_BASE_ADDRESS+0x18 /* E OnCE EE pins Cont rol re gister * /
#define PC_EX REG_BASE_ADDRESS+0x1c /* E OnCE Exc eption PC regis ter */
#define EDCA0_CTRL REG_BASE_ADDRESS+0x40 /* E OnCE EDC A #0 Cont rol re gister * /
#define EDCA1_CTRL REG_BASE_ADDRESS+0x44 /* E OnCE EDC A #1 Cont rol re gister * /
#define EDCA2_CTRL REG_BASE_ADDRESS+0x48 /* E OnCE EDC A #2 Cont rol re gister * /
#define EDCA3_CTRL REG_BASE_ADDRESS+0x4c /* E OnCE EDC A #3 Cont rol re gister * /
#define EDCA4_CTRL REG_BASE_ADDRESS+0x50 /* E OnCE EDC A #4 Cont rol re gister * /
#define EDCA5_CTRL REG_BASE_ADDRESS+0x54 /* E OnCE EDC A #5 Cont rol re gister * /
#define EDCA0_REFA REG_BASE_ADDRESS+0x60 /* E OnCE EDC A #0 Refe rence Value A */
#define EDCA1_REFA REG_BASE_ADDRESS+0x64 /* E OnCE EDC A #1 Refe rence Value A */
#define EDCA2_REFA REG_BASE_ADDRESS+0x68 /* E OnCE EDC A #2 Refe rence Value A */
#define EDCA3_REFA REG_BASE_ADDRESS+0x6c /* E OnCE EDC A #3 Refe rence Value A */
#define EDCA4_REFA REG_BASE_ADDRESS+0x70 /* E OnCE EDC A #4 Refe rence Value A */
#define EDCA5_REFA REG_BASE_ADDRESS+0x74 /* E OnCE EDC A #5 Refe rence Value A */
#define EDCA0_REFB REG_BASE_ADDRESS+0x80 /* E OnCE EDC A #0 Refe rence Value B */
#define EDCA1_REFB REG_BASE_ADDRESS+0x84 /* E OnCE EDC A #1 Refe rence Value B */
#define EDCA2_REFB REG_BASE_ADDRESS+0x88 /* E OnCE EDC A #2 Refe rence Value B */
#define EDCA3_REFB REG_BASE_ADDRESS+0x8c /* E OnCE EDC A #3 Refe rence Value B */
#define EDCA4_REFB REG_BASE_ADDRESS+0x90 /* E OnCE EDC A #4 Refe rence Value B */
#define EDCA5_REFB REG_BASE_ADDRESS+0x94 /* EOnCE ED CA #5 Ref erence Value B */
#define EDCA0_MASK REG_BASE_ADDRESS+0xc0 /* EOnCE ED CA #0 Mas k Regi ster */
#define EDCA1_MASK REG_BASE_ADDRESS+0xc4 /* EOnCE ED CA #1 Mas k Regi ster */
#define EDCA2_MASK REG_BASE_ADDRESS+0xc8 /* EOnCE ED CA #2 Mas k Regi ster */
#define EDCA3_MASK REG_BASE_ADDRESS+0xcc /* EOnCE ED CA #3 Mas k Regi ster */
#define EDCA4_MASK REG_BASE_ADDRESS+0xd0 /* EOnCE ED CA #4 Mas k Regi ster */
#define EDCA5_MASK REG_BASE_ADDRESS+0xd4 /* EOnCE ED CA #5 Mas k Regi ster */
#define EDCD_CTRL REG_BASE_ADDRESS+0xe0 /* EOnCE ED CD Contro l regi ster */
#define EDCD_REF REG_BASE_ADDRESS+0xe4 /* EOnCE ED CD Refere nce Va lue */
#define EDCD_MASK REG_BASE_ADDRESS+0xe8 /* EOnCE ED CD Mask r egiste r */
#define ECNT_CTRL REG_BASE_ADDRESS+0x100 /* EOnCE C ounter Co ntrol register */
#define ECNT_VAL REG_BASE_ADDRESS+0x104 /* EOnCE C ounter Va lue re gister * /
#define ECNT_EXT REG_BASE_ADDRESS+0x108 /* EOnCE E xtension Counte r Value */
#define ESEL_CTRL REG_BASE_ADDRESS+0x120 /* EOnCE S elector C ontrol registe r */
#define ESEL_DM REG_BASE_ADDRESS+0x124 /* EOnCE S elector D M Mask */
#define ESEL_DI REG_BASE_ADDRESS+0x128 /* EOnCE S elector D I Mask */
#define ESEL_RST REG_BASE_ADDRESS+0x12c /* EOnCE S elector R ST Mas k */
#define ESEL_ETB REG_BASE_ADDRESS+0x130 /* EOnCE S elector E TB Mas k */
#define ESEL_DTB REG_BASE_ADDRESS+0x134 /* EOnCE S elector D TB Mas k */
#define TB_CTRL REG_BASE_ADDRESS+0x140 /* EOnCE T race Buff er Con trol reg ister */
#define TB_RD REG_BASE_ADDRESS+0x144 /* EOnCE T race Buff er Rea d Pointe r */
#define TB_WR REG_BASE_ADDRESS+0x148 /* EOnCE T race Buff er Wri te Point er */
#define TB_BUFF REG_BASE_ADDRESS+0x14c /* EOnCE T race Buff er */
#define TRAP_EXCP EXCP_TABLE /* trap instru ction ex ception * /
#define ILL_EXCP EXCP_TABLE+0x80 /* illegal set or illegal instruction exception */
#define DBG_EXCP EXCP_TABLE+0xc0 /* debug exceptio n (eonce) */
#define OVFL_EXCP EXCP_TABLE+0x100 /* overf low exce ption */
#define AUTO_NMI_EXCP EXCP_TABLE+0x180 /* defau lt nmi e xception vector */
#define AUTO_EXT_EXCP EXCP_TABLE+0x1c0 /* defau lt exter nal excep tion * /
#define NMI_EXCP EXCP_TABLE+0x280 /* nmi e xception vector ( arbitr ary addr ess) * /
#define EXT_EXCP EXCP_TABLE+0x2c0 /* exter nal exce ption (a rbitra ry addre ss) */
#endif