130
µ
PD17062
11.9.3 Interrupt Level Restriction by Address Stack Register
The return address at control return from interrupt processing is automatically saved in the address stack
register.
The address stack register can use the six levels from ASR0 to ASR5 as described in Chapter 4. Because
the interrupt sources are the INTNC pin, timer, VSYNC pin, and serial interface, the multiple interrupt level is
unlimited when the address stack register is used only for interrupts.
However, because the address stack register is also used to save the return address at subroutine calling,
multiple interrupt levels are limited according to the levels of the address stack register used for subroutine
calling.
For example, if four levels are used for subroutine calling, only two levels of the multiple interrupts shown
in Fig. 11-10 can be used.
Fig. 11-10 Address Stack Register Operation
ASR0
ASR1
ASR2
ASR3
ASR4
ASR5
ASR6
ASR7
× × × ×
Undefined
Undefined
Undefined
Undefined
Undefined
MAIN
× × × ×
× × × ×
Undefined
Undefined
Undefined
Undefined
SUB1
MAIN
× × × ×
× × × ×
Undefined
Undefined
Undefined
SUB2
SUB1
MAIN
× × × ×
× × × ×
Undefined
Undefined
SUB3
SUB2
SUB1
MAIN
× × × ×
× × × ×
Undefined
AAA
SUB3
SUB2
SUB1
MAIN
× × × ×
× × × ×
SUB4
AAA
SUB3
SUB2
SUB1
MAIN
× × × ×
× × × ×
SUB4
AAA
SUB3
SUB2
SUB1
MAIN
× × × ×
× × × ×
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
× × × ×
× × × ×
SUB4
AAA
SUB3
SUB2
SUB1
MAIN
× × × ×
RET
BBB:SUB4:AAA:SUB3:SUB2:SUB1:
MAIN:
Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8
Stack
pointer
SP
Main routine Subroutine
1
Subroutine
2
Subroutine
3
Interrupt
A
Subroutine
4
Interrupt
B
Subroutine
5
Because the contents of the address stack register
(ASR0) are always undefined when the stack pointer
is 0, the return addressof the RET instruction also
becomes undefined.
Address stack
register