145
µ
PD17062
12.4.3 If the BTM0CY flag is checked at the same time with a CE reset
As described in Section 12.4.2, a CE reset occurs at the same time the BTM0CY flag is set to 1.
If the BTM0CY flag read instruction happens to occur at the same time a CE reset occurs, the BTM0CY flag
read instruction takes precedence.
Once a CE pin goes from a low to a high, if the setting of the BTM0CY flag (at the positive-going edge of
the timer carry FF set pulse) and a BTM0CY flag read instruction occur at the same time, a CE reset occurs
next time the BTM0CY flag is set.
This operation is shown in Fig. 12-7.
Fig. 12-7 Operation That Occurs When a CE Reset and a BTM0CY Flag Read Instruction Coincide
So, if your program checks the BTM0CY flag cyclically and the BTM0CY flag check time interval coincides
with the BTM0CY flag setting time interval, a CE reset will not occur forever.
Note the following point:
Because one instruction cycle is 2
µ
s (1/500 kHz), a program that checks the BTM0CY flag once at every 500
instructions reads the BTM0CY flag at every 1 ms (2
µ
s × 500).
Under this condition, whichever timer interval set pulse, 5 ms or 100 ms, is selected, a CE reset will not
occur for ever, once the setting and checking of the BTM0CY flag occur at the same time.
To be specific, avoid creating a cyclic program that satisfies the following condition.
tSET × 500 = n (n is any integer)
x
where tSET : BTM0CY flag setting time interval
x : BTM0CY flag read instruction cycle time x number of steps
In other words, the program should not contain x steps when the above calculation produces any integer.
SKT 1
BTM0CY
SKT 1
BTM0CY
CE reset
SKT1 BTM0CY
(PEEK…) (SKT…)
CE pin
Timer carry FF
set pulse
BTM0CY flag
Timer carry FF set pulse
BTM0CY flag
Instruction
Built-in macro
2
s
If the BTM0CY flag is read
during this period, a CE
reset is deferred by one cycle.
Normally, the program starts at address 0000H at this
point, but a CE reset does occur because the program to
read the BTM0CY flag also happens to run.
PEEK WR, . MF. BTM0CY SHR 4
SKT WR, #, DF. BTM0CY AND 000FH
µ