79
µ
PD17062
9.9 PLL REFERENCE MODE SELECTION REGISTER (13H)
9.10 SETTING OF INTNC PIN ACCEPTANCE PULSE WIDTH (15H)
b
3
b
2
b
1
b
0
PLLRFCK3 PLLRFCK2 PLLRFCK0
13H
PLLRFCK1
0010
0011
0110
1111
0111
1010
1011
1110
6.25 kHz
12.5 kHz
25 kHz
PLL disabled
Not to be set
Reference frequency f
r
setting
Fixed at 1
b
3
b
2
b
1
b
0
INTNCMD3 INTNCMD2 INTNCMD0
15H
INTNCMD1
000
001
010
011
100
Edge (no noise canceler)
200
s
2 ms
Setting of INT
NC
pin acceptance pulse width
Fixed at 0
4 ms
400 s
µ
µ