CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15331EJ4V1UD 55
Figure 3-6. Data Memory Addressing (
µ
PD78F9488)
Special function registers
256 × 8 bits
Internal high-speed RAM
1024 × 8 bits
LCD display RAM
28 × 4 bits
F F F F H
8 0 0 0 H
7 F F F H
0 0 0 0 H
Direct addressing
Register indirect addressing
Based addressing
F F 0 0 H
F E F F H
F F 2 0 H
F F 1 F H
F E 2 0 H
F E 1 F H
SFR addressing
Short direct addressing
F B 0 0 H
F A F F H
F A 1 C H
F A 1 B H
Reserved
F A 0 0 H
F 9 F F H
Reserved
Flash memory
32768 × 8 bits