Panasonic MN103001G/F01K

Fig. 8-7-1 Address Format When Accessing External Memory.............................................. 8-26

Fig. 8-7-2 Space Partitioning....................................................................................................8-27

Fig. 8-12-1 Internal I/O Space Access .......................................................................................8-31

Fig. 8-13-1 Access Timing on a 16-bit Bus with Fixed Wait States,

in Synchronous Mode and in Address/Data Separate Mode

(MCLK = SYSCLK multiplied by 4)...................................................................... 8-33

Fig. 8-13-2 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and

in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2).................. 8-34

Fig. 8-13-3 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous

Mode and in Address/Data Separate Mode (MCLK = SYSCLK).......................... 8-34

Fig. 8-13-4 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and

in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 4).................. 8-35

Fig. 8-13-5 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and

in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2).................. 8-36

Fig. 8-13-6 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and

in Address/Data Separate Mode (MCLK = SYSCLK) ...........................................8-36

Fig. 8-13-7 Access Timing on a 16-bit Bus in Asynchronous Mode and in

Address/Data Separate Mode (MCLK = SYSCLK multiplied by 4)...................... 8-37

Fig. 8-13-8 Access Timing on a 16-bit Bus in Asynchronous Mode and in

Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2)...................... 8-38

Fig. 8-13-9 Access Timing on a 16-bit Bus in Asynchronous Mode and

in Address/Data Separate Mode (MCLK = SYSCLK) ...........................................8-38

Fig. 8-13-10 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and

in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 4).................. 8-39

Fig. 8-13-11 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and

in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2).................. 8-40

Fig. 8-13-12 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and

in Address/Data Separate Mode (MCLK = SYSCLK) ...........................................8-40

Fig. 8-13-13 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and

in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 4).................. 8-42

Fig. 8-13-14 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and

in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2).................. 8-43

Fig. 8-13-15 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and

in Address/Data Separate Mode (MCLK = SYSCLK) ...........................................8-44

Fig. 8-13-16 Access Timing on a 8-bit Bus in Asynchronous Mode and

in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 4).................. 8-45

Fig. 8-13-17 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and

in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4)................ 8-46

Fig. 8-13-18 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and

in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2)................ 8-47

Fig. 8-13-19 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and

in Address/Data Multiplex Mode (MCLK = SYSCLK) .........................................8-47

Fig. 8-13-20 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and

in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4)................ 8-49