Philips Semiconductors Product specification
SA5205AWide-band high-frequency amplifier
1997 Nov 07 7

THEORY OF OPERATION

The design is based on the use of multiple feedback loops to
provide wide-band gain together with good noise figure and terminal
impedance matches. Referring to the circuit schematic in Figure 17,
the gain is set primarily by the equation:
VOUT
VIN RF1 RE1
RE1
(1)
which is series-shunt feedback. There is also shunt-series feedback
due to RF2 and RE2 which aids in producing wideband terminal
impedances without the need for low value input shunting resistors
that would degrade the noise figure. For optimum noise
performance, RE1 and the base resistance of Q1 are kept as low as
possible while RF2 is maximized.
The noise figure is given by the following equation:
NF =
10 log

1

rbRE1 KT
2qlC1
RO

dB (2)
where IC1=5.5mA, RE1=12Ω, rb=130Ω, KT/q=26mV at 25°C and
R0=50 for a 50Ω system and 75 for a 75Ω system.
The DC input voltage level VIN can be determined by the equation:
VIN=VBE1+(IC1+IC3) RE1
where RE1=12Ω, VBE=0.8V, IC1=5mA and IC3=7mA (currents rated
at VCC=6V).
Under the above conditions, VIN is approximately equal to 1V.
Level shifting is achieved by emitter-follower Q3 and diode Q4 which
provide shunt feedback to the emitter of Q1 via RF1. The use of an
emitter-follower buffer in this feedback loop essentially eliminates
problems of shunt feedback loading on the output. The value of
RF1=140Ω is chosen to give the desired nominal gain. The DC
output voltage VOUT can be determined by:
VOUT=VCC-(IC2+IC6)R2,(4)
where VCC=6V, R2=225Ω, IC2=8mA and IC6=5mA.
From here it can be seen that the output voltage is approximately
3.1V to give relatively equal positive and negative output swings.
Diode Q5 is included for bias purposes to allow direct coupling of
RF2 to the base of Q1. The dual feedback loops stabilize the DC
operating point of the amplifier.
The output stage is a Darlington pair (Q6 and Q2) which increases
the DC bias voltage on the input stage (Q1) to a more desirable
value, and also increases the feedback loop gain. Resistor R0
optimizes the output VSWR (Voltage Standing Wave Ratio).
Inductors L1 and L2 are bondwire and lead inductances which are
roughly 3nH. These improve the high-frequency impedance
matches at input and output by partially resonating with 0.5pF of pad
and package capacitance.
VIN L2
3nH Q1 Q4
RF1
140
RE1
12
RF2
200
Q5
RE2
12
R3
140
Q6
10 3nH
L2
VOUT
R2
225
VCC
R1
650 R0
Q3
Q2
SR00231
Figure 17. Schematic Diagram