4-3 PLL CIRCUITS
4-3-1 PLL CIRCUIT (MAIN AND LOGIC UNITS)
A PLL circuit provides stable oscillation of the transmit fre- quency and receive 1st LO frequency. The PLL output com- pares the phase of the divided VCO frequency to the refer- ence frequency. The PLL output frequency is controlled by the divided ratio
An oscillated signal from the TX and
The lock voltage is also used for the receiver tunable band- pass filters to match the filter’s center frequency to the desired receive frequency. The lock voltage is passed through the loop filter (Q2), and then applied to the DC amplifier (Q10). The amplified signal is applied to the CPU (LOGIC unit; IC7, pin 98) via the “LVIN” signal. The signal is analyzed at the CPU, and then applied to bandpass filters
4-3-2 VCO CIRCUIT (MAIN UNIT)
The VCO circuit contains a separate
A portion of the signal from LO amplifier (Q9) is amplified at the buffer amplifier (Q12) and is then fed back to the PLL IC (IC1, pin 6) as the comparison signal.
POWER SUPPLY CIRCUITS | ||
VOLTAGE LINE | ||
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LINE |
| DESCRIPTION |
HV |
| The voltage from the power supply. |
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| The same voltage as HV line which is controlled |
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| by the HVSW circuit (Q28, Q30, Q31). When the |
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| [POWER] switch is pushed, the CPU outputs the |
SWHV |
| “PWRON” control signal via the expander IC |
| (IC2). The signal is applied to the HVSW circuit | |
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| to turn the circuit ON. |
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| The output voltage is applied to the drive ampli- |
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| fier (Q18), +8V regulator circuit (IC7), etc. |
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| Common 5 V for the CPU converted from the HV |
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| line by the C5V regulator circuit (IC8). The circuit |
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| outputs the voltage regardless of the power |
C5V |
| ON/OFF condition. |
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| The output voltage is applied to the EEPROM |
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| (LOGIC UNIT; IC5), CPU (LOGIC UNIT; IC7), |
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| etc. |
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| Common 8 V converted from the 13.8 V line by |
+8V |
| the +8V regulator circuit (IC7). |
| The output voltage is applied to the LO (Q9) and | |
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| buffer (Q11) amplifiers, etc. |
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+5V |
| Common 5 V converted from the +8 V line by the |
| +5V regulator circuit (Q21, Q22). | |
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| Transmit 8 V controlled by the T8V regulator cir- |
T8 |
| cuit (Q14, Q15) using the “TXC” signal from the |
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| I/O expander IC (IC2). |
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| Receive 5 V controlled by the R5V regulator cir- |
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| cuit (Q25) using “RXC” signal from the I/O |
R5V |
| expander IC (IC2). |
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| The output voltage is applied to the FM IC IC |
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| (IC4), IF (Q16) and RF (Q27) amplifiers, etc. |
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• PLL CIRCUIT
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| TX VCO |
| to transmitter circuit | |
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| Q11 |
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| Q6, | D6 | ||
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| Buff. | |||
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| D2, | to 1st mixer circuit (Q19) | ||
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| D4 | Q9 | ||
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| RX VCO | LO | D7 | |
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| Q12 |
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| Q7, | TX/RX | ||
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Loop |
| Buff. | switch | ||
Q2 | D5 | ||||
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filter |
| IC1 (PLL IC) |
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9 | Phase | Programable | Prescaler | 6 |
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| detector | divider |
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| Reference |
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| 2 | PLLCK |
X1 |
| Shift register | 3 | |||
| PLLDATA | |||||
25.25 MHz | divider |
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| 4 | PLLSTB |
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1 |
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| 25.25 MHz 2nd LO signal | ||
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| to the 2nd IF IC (IC4, pin 2) |
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