Rev. 1.00, 05/04, page 531 of 544
22.7.2 Control Signal Timing
The control signal timings are shown below.
tRESW
tRESS
φ
tRESS
RES
Figure 22.8 Reset Input Timing
t
IRQS
φ
t
NMIS
t
NMIH
IRQi
Edge input
(i = 7 to 0)
NMI
t
IRQS
t
IRQH
IRQi
(i = 7 to 0)
IRQi
Level input
(i = 7 to 0)
t
NMIW
t
IRQW
Figure 22.9 Interrupt Input Timing