Renesas HD74AC182 Truth Table

HD74AC182

Rev.2.00, Jul.16.2004, page 3 of 6

Cn + x = G0 + P0Cn

Cn + y = G1 + P1G0 + P1P0Cn

Cn + z = G2 + P2G1 + P2P1G0 + P2P1P0Cn

G= G3 + P3G2 + P3P2G1 + P3P2P1G0

P= P3P2P1P0

Also, the HD74AC182/HD74ACT182 can be used with binary ALUs in an active Low or active High input operand

mode. The connections (Figure a) to and from the ALU to the carry lookahead generator are identical in both cases.

Carries are rippled between lookahead blocks. The critical speed path follows the circled numbers. There are several

possible arrangements for the carry interconnects, but all achieve about the same speed. A 28-bit ALU is formed by

dropping the last HD74AC182/HD74ACT182.

Truth Table

Inputs Outputs

CnG

G0P

P0G

G1P

P1G

G2P

P2G

G3P

P3Cn + x Cn + y Cn + z G

XHH L

LHX L

XLX H

HXL H

XXXHH L

XHHHX L

LHXHX L

XXXLX H

XLXXL H

HXLX L H

XXXXXHH L

XXXHHHX L

XHHHXHX L

LHXHXHX L

XXXXXLX H

XXXLXXL H

XLXXLXL H

HXLX LXL H

X XXXXHH H

X XXHHHX H

XHHHXHX H

HHXHXHX H

X XXXXLX L

XXXLXXL L

XLXXLXL L

LXLXLXL L

HXXX H

XHXX H

XXHX H

XXXH H

LLLL L

H : High Voltage Level

L : Low Voltage Level

X : Immaterial