Renesas M3062NT3-RPD-E (3) Multiplex Bus Timing

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(3) Multiplex Bus Timing

Table 5.4 and Figure 5.3 show the bus timing in memory expansion and microprocessor modes (with

wait, accessing external area, using multiplex bus).

Table 5.4 Memory expansion and microprocessor modes (with wait, accessing external area, using multiplex bus)

*1 Calculated by the following formula accord-

ing to the frequency of BCLK.

th(RD-AD)= +0 [ns]

109

f(BCLK)x2

th(WR-AD)= +0 [ns]

109

f(BCLK)x2

th(RD-CS)= +0 [ns]

109

f(BCLK)x2

th(WR-CS)= +0 [ns]

109

f(BCLK)x2

th(DB-WR)= -50 [ns]

109x3

f(BCLK)x2

th(WR-DB)= +0 [ns]

109

f(BCLK)x2

th(AD-ALE)= -40 [ns]

109

f(BCLK)x2

*2 Calculated by the following formula accord-

ing to the frequency of BCLK.

th(WR-AD)= -6 [ns]

109

f(BCLK)x2

th(WR-CS)= -6 [ns]

109

f(BCLK)x2

th(WR-DB)= -12 [ns]

109

f(BCLK)x2

td(BCLK-AD)

th(BCLK-AD)

th(RD-AD)

th(WR-AD)

td(BCLK-CS)

th(BCLK-CS)

th(RD-CS)

th(WR-CS)

td(BCLK-RD)

th(BCLK-RD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

th(WR-DB)

td(BCLK-ALE)

th(BCLK-ALE)

td(AD-ALE)

th(ALE-AD)

td(AD-RD)

td(AD-WR)

tdz(RD-AD)

Address output delay time

Address output hold time (BCLK standard)

Address output hold time (RD standard)

Address output hold time (WR standard)

Chip-select output delay time

Chip-select output hold time (BCLK standard)

Chip-select output hold time (RD standard)

Chip-select output hold time (WR standard)

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

Data output delay time (BCLK standard)

Data output hold time (BCLK standard)

Data output delay time (WR standard)

Data output hold time (WR standard)

ALE output delay time (BCLK standard)

ALE output hold time (BCLK standard)

ALE output delay time (Address standard)

ALE output hold time (Address standard)

After address RD signal output delay time

After address WR signal output delay time

Address output floating start time

Symbol Item

Actual MCU

[ns] This product

[ns]

Min.

Min. Max.

4

(*1)

(*1)

4

(*1)

(*1)

0

0

4

(*1)

(*1)

-4

(*1)

30

0

0

50

50

40

40

50

40

8

See left

See left

(*2)

See left

(*2)

(*2)

See left

See left

See left

(*2)

(*2)

See left

See left

See left

-4

-3

Max.

See left

See left

See left

See left

See left

See left

17

Contents

Main Page Preface To use the product properly Precautions for Safety When using outside Japan Contents Page Page Terminology Page Page Chapter 1. Precautions for Safety WARNING IMPORTANT CAUTION WARNING Warning for Installation: Warnings for Use Environment: Caution to Be Taken for Modifying This Product: Cautions to Be Taken for Handling This Product: Page Note on Clock Supply to the MCU: Note on RDY* Input: Notes on HOLD* Input: Note on NMI* Input: Note on RESET* Input: Notes on MAP References and Settings: Note on Stack Area: Note on Operation When Not Executing the User Program: Note on Making an MCU file: Notes on Maskable Interrupts: Notes on Address-Match Interrupt: Note on BRK Instruction and BRK Interrupt: Notes on Software and Hardware Breaks: Note on Stop and Wait Modes: Note on Watchdog Function: Note on DMA Transfer: Note on Pullup Control: Note on Reading Internal Resources of the MCU: Note on Protect Register (PRC2): Note on Accessing Address 00000h: Note on Differences Between the Actual MCU and Emulator: Page Page Chapter 2. Preparation 2.2 Other Tool Products Required for Development Chapter 2. Preparation 2.1 Package Components 2.3 Name of Each Part (1) System Configuration (2) Inside of the Emulation Pod 2.4 When Using This Product for the First Time (1) Making an MCU File (2) Setting the Work Area (3) Downloading Firmware (4) Self-check Page Chapter 3. Setting Up 3.1 Removing and Closing the Upper Cover When Removing and Closing the Upper Cover: 3.2 Each Setting 3.3 Selecting Clock Supply and Replacing Oscillator Circuit Boards (1) Clock Supply to the MCU Note on Changing the Clock Supply: (2) Using the Oscillator Circuit on the Target System Page (4) Replacing Oscillator Circuit Boards 3.4 Switch Settings (1) Toggle Switches SW1 to SW5 on the M30620T3-PRT Board (MCU-dependent 1) Table 3.2 Switch settings of the M3062NT3-RPD-E (1/3) Table 3.3 Switch settings of the M3062NT3-RPD-E (2/3) Note on Switch Settings: Always shut OFF power before changing switch settings. Note on BYTE and CNVss Switch Settings: Switch settings of the BYTE and CNVss are for debugging without the target system connected. (2) Jumper Switches JP1 and JP2 on the M30620T3-PRT Board (MCU-dependent 1) Note on Switch Settings: 3.5 Installing and Removing Pullup Resistors Note on Installing and Removing Pullup Resistors: 3.6 A-D Conversion Bypass Capacitors Note on the A-D Converter Function: 3.7 Connecting the PC4701 (1) Connecting the Cable to the PC4701 Notes on Connecting the Cable: Note on Securing the Screws: Page 3.8 Connecting the Target System Figure 3.12 Connecting the target system Emulation pod probe (1) Connecting to a 100-pin LCC Socket (2) Connecting to an 80-pin 0.65-mm-pitch Foot Pattern (Part 1) (3) Connecting to an 80-pin 0.65-mm-pitch Foot Pattern (Part 2) (4) Connecting to a 100-pin 0.65-mm-pitch Foot Pattern (Part 1) (5) Connecting to a 100-pin 0.65-mm-pitch Foot Pattern (Part 2) (6) Connecting to a 100-pin 0.65-mm-pitch Foot Pattern (Part 3) (7) Connecting to a 100-pin 0.5-mm-pitch Foot Pattern (Part 1) (8) Connecting to a 100-pin 0.5-mm-pitch Foot Pattern (Part 2) (9) Connecting to a 100-pin 0.5-mm-pitch Foot Pattern (Part 3) (10) Connecting to a 100-pin 0.4-mm-pitch Foot Pattern Page Page Chapter 4. Usage 4.1 Turning On the Power (1) Checking Connections of the Emulator System (2) Turning ON/OFF the Power Notes on Power Supply: Note on Memory Expansion and Microprocessor Modes: Note on the Target Status POWER LED: Note on the Target Status CLOCK LED: 4.2 Downloading Firmware (1) When It is Necessary to Download Firmware Note on Downloading Firmware: 4.3 Self-check (1) Self-check Procedure Note on Self-check: (2) If an Error is Detected in the Self-check Page Page Chapter 5. Specifications 5.1 Specifications 5.2 Operation Timing in Memory Expansion and Microprocessor Modes (1) Separate Bus, No-Wait *1 Calculated by the following formula according to the frequency of BCLK. Page (2) Separate Bus, With Wait, Accessing External Memory Area f(BCLK) *1 Calculated by the following formula according to the frequency of BCLK. Page (3) Multiplex Bus Timing *1 Calculated by the following formula accord- ing to the frequency of BCLK. 109x3 *2 Calculated by the following formula accord- ing to the frequency of BCLK. Page Figure 5.4 Timing requirements (4) Timing Requirements Table 5.5 and Figure 5.4 show the timing requirements. Table 5.5 Timing requirements Page Table 5.6 Electrical characteristics of the 74HC4066 Table 5.7 Electrical characteristics of the FPGA Page Figure 5.7 External dimensions of the converter board M30800T-PTC and a sample foot pattern (2) External Dimensions of the Converter Board M30800T-PTC Page Page Chapter 6. Troubleshooting 6.1 Flowchart to Remedy the Troubles Figure 6.1 Flowchart to remedy troubles 6.2 When the Emulator Debugger Does Not Start Up Properly (1) When the LED Display of the PC4701 is Abnormal Table 6.1 LED's abnormal display and its checkpoints See the PC4701 user's manual. See "3.7 Connecting the PC4701" (page 39). (2) Program Window is Not Displayed at Debugger Startup (Target Connected) Table 6.2 Checkpoints of errors when starting up the emulator debugger (target connected) (3) Program Window is Not Displayed at Debugger Startup (Target Not Connected) Table 6.3 Checkpoints of errors when starting up the emulator debugger (target not connected) 6.3 How to Request for Support Page Page Chapter 7. Maintenance and Guarantee 7.1 Maintenance 7.2 Guarantee 7.3 Repair Provisions 7.4 How to Request for Repair Note on Transporting the Product: