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Renesas M306H2T-RPD-E (3) Multiplex Bus, With Wait, Accessing External Memory Area

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(3) Multiplex Bus, With Wait, Accessing External Memory Area

Table 5.4 and Figure 5.3 show the bus timing in the memory expansion and microprocessor modes

(with wait, accessing external memory area and using multiplex bus).

Table 5.4 Memory expansion and microprocessor modes (with wait, multiplex bus)

Th (RD-AD) = 109

f(BCLK)x2 [ns]

Th (WR-AD) = 109

f(BCLK)x2 [ns]

Th (RD-CS) = 109

f(BCLK)x2 [ns]

Th (WR-CS) = 109

f(BCLK)x2 [ns]

Td (DB-WR) = 109x3

f(BCLK)x2 -40 [ns]

Th (WR-DB) = 109

f(BCLK)x2 [ns]

Td (AD-ALE) = 109

f(BCLK)x2 -25 [ns]

*2 Calculated by the following formulas accord-

ing to the frequency of BCLK.

Th (RD-AD) = 109

f(BCLK)x2 -3 [ns]

*1 Calculated by the following formulas accord-

ing to the frequency of BCLK.

Th (WR-AD) = 109

f(BCLK)x2 -3 [ns]

Td (BCLK-AD)

Th (BCLK-AD)

Th (RD-AD)

Th (WR-AD)

Td (BCLK-CS)

Th (BCLK-CS)

Th (RD-CS)

Th (WR-CS)

Td (BCLK-RD)

Th (BCLK-RD)

Td (BCLK-WR)

Th (BCLK-WR)

Td (BCLK-DB)

Th (BCLK-DB)

Td (DB-WR)

Th (WR-DB)

Td (BCLK-ALE)

Th (BCLK-ALE)

Td (AD-ALE)

Th (ALE-AD)

Td (AD-RD)

Td (AD-WR)

Tdz (RD-AD)

Address output delay time

Address output hold time (BCLK standard)

Address output hold time (RD standard)

Address output hold time (WR standard)

Chip-select output delay time

Chip-select output hold time (BCLK standard)

Chip-select output hold time (RD standard)

Chip-select output hold time (WR standard)

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

Data output delay time (BCLK standard)

Data output hold time (BCLK standard)

Data output delay time (WR standard)

Data output hold time (WR standard)

ALE output delay time (BCLK standard)

ALE output hold time (BCLK standard)

ALE output delay time (Address standard)

ALE output hold time (Address standard)

After address RD signal output delay time

After address WR signal output delay time

Address output floating start time

Min.

4

(*1)

(*1)

4

(*1)

(*1)

0

0

4

(*1)

(*1)

-4

(*1)

50

0

0

Max.

25

25

25

25

40

25

8

Min.

(*2)

(*2)

Max.

Actual MCU

[ns] This product

[ns]

Symbol Item

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Contents

Main Page Preface To use the product properly Precautions for Safety When using outside Japan Contents Page Page Page Page Chapter 1. Precautions for Safety WARNING IMPORTANT CAUTION Note on Malfunctions in the PC4701 System: WARNING Warning for Installation: Warnings for Use Environment: Caution to Be Taken for Modifying This Product: Cautions to Be Taken for Handling This Product: Notes on Downloading Firmware: Notes on Target System: Note on When the Emulator Debugger Ends: Note on Final Evaluation: Notes on Stack Area: Note on Setting the Work Area: Notes on MAP References and Settings: Note on RESET* Input: Note on Clock Supply to the MCU: Note on HOLD* Input: Notes on NMI* Input: Note on RDY* Input: Note on Software Reset: Notes on Address Match Interrupt: Notes on Interruption: Note on BRK Instruction and BRK Instruction Interruption: Note on Stop and Wait Modes: Note on Protect Resistor (PRC2): Note on Commands that Access the Single-step Interrupt Vector Area: Notes on Software Breaks and Hardware Breaks: Note on DMA Transfer: Notes on Pullup Control Resistor: Note on Reading Internal Resources of an MCU: Notes on Watchdog Function: Note on Differences between Actual MCUs and the Emulator: Table 1.3 Differences of outputs between actual MCUs and this product (when executing program) Table 1.4 Differences of outputs between actual MCUs and this product (in stop mode) Table 1.5 Differences of outputs between actual MCUs and this product (in wait mode) Table 1.6 Outputs of this product when the user program is stopping Page Page Chapter 2. Preparation 2.1 Terminology 2.2 Package Components 2.3 Other Tool Products Required for Development 2.4 Name of Each Part (1) System Configuration (2) Inside of the Emulation Pod 2.5 When Using the Emulator for the First Time Page Chapter 3. Setting Up 3.1 Removing the Upper Cover When Removing the Upper Cover: Page Table 3.1 Switch settings of the M306H2T-RPD-E (1/4) Table 3.2 Switch settings of the M306H2T-RPD-E (2/4) Switch Signal Setting Description system. (Uses P8 6 /X COUT pin as port P8 P86/XCOUTSW5 Note on Switch Settings: Table 3.3 Switch settings of the M306H2T-RPD-E (3/4) Table 3.4 Switch settings of the M306H2T-RPD-E (4/4) Page 3.3 Selecting Clock Supply Notes on Changing the Clock Supply: (1) Using the Oscillator Circuit on the Target System Notes on External Clock: Page (3) Replacing the Oscillator Circuit Boards 3.4 A-D Conversion Bypass Capacitor Note on the A-D Converter: Page 3.6 Connecting the PC4701 (1) Connecting the Cable to the PC4701 Note on Connecting the Cable: Note on Securing the Screws: Page 3.7 Connecting the Target System Notes on Connecting the Target System: 3.8 Making an MCU File for PD30 Page Chapter 4. Usage 4.1 Turning On the Power (1) Checking the Connection of the Emulator System (2) Turning On the Power Notes on Power Supply: Note on Memory Expansion and Microprocessor Modes: Note on CLOCK LED: 4.2 Downloading Firmware (1) When It is Necessary to Download Firmware (2) Downloading Firmware in the Maintenance Mode Note on Downloading Firmware: 4.3 Self-checks (1) Self-check Procedure (2) If an Error is Detected in Self-checks Note on Self-checks: Page Page Chapter 5. Specifications 5.1 Specifications 5.2 Operation Timing in the Memory Expansion and Microprocessor Modes (5 V) (1) Separate Bus, No-Wait *1 Calculated by the following formula according to the frequency of BCLK. Figure 5.1 Memory expansion and microprocessor modes (no-wait) (2) Separate Bus, With Wait, Accessing External Memory Area *1 Calculated by the following formula according to the frequency of BCLK. Figure 5.2 Memory expansion and microprocessor modes (with wait) (3) Multiplex Bus, With Wait, Accessing External Memory Area *2 Calculated by the following formulas accord- ing to the frequency of BCLK. *1 Calculated by the following formulas accord- ing to the frequency of BCLK. Figure 5.3 Memory expansion and microprocessor modes (with wait, multiplex bus) (4) Timing Requirements Figure 5.4 Timing requirements *1 Minimum 7 ns (The definition is different from that of actual MCUs. For details, see Figure 5.5.) Figure 5.5 Timing requirements 5.3 Electrical Characteristics 5.4 Connection Diagram Page Page Page Chapter 6. Troubleshooting 6.1 Flowchart to Remedy the Troubles Figure 6.1 Flowchart to remedy troubles 6.2 When the Emulator Debugger Does Not Start Up Properly (1) When the LED Display of the PC4701 is Abnormal Table 6.1 LED's abnormal display and its checkpoints See the user's manual of the PC4701. See "3.6 Connecting the PC4701" (page 41). (2) Errors Occur When the Emulator Debugger Starts Up (When the target system is connected) Table 6.2 Checkpoints of errors when starting up the emulator debugger (target is connected) (3) Errors Occur When the Emulator Debugger Starts Up (When the target system is not connected) Table 6.3 Checkpoints of errors when starting up the emulator debugger (target is not connected) 6.3 Operation Differs from That of Actual MCUs Page Chapter 7. Maintenance and Guarantee 7.1 Maintenance 7.2 Guarantee 7.3 Repair Provisions 7.4 How to Request for Repair Note on Transporting the Product: