Renesas M34514T-MCU Figure 4.5 Connector J3 pin layout

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(1) Connector J3
Table 4.5 lists the pin assignments of the 100-wire half-pitch connector (J3) for connecting the
PCA4029. And Figure 4.5 shows the connector J3 pin layout.
Table 4.5 Pin assignments of the connector J3
Figure 4.5 Connector J3 pin layout
Note: "I" in the direction column denotes "Input"; "O" denotes "Output"; "I/O" denotes "Input/
output"; "-" denotes "Not connected".
Line A Line B Line C Line D
Pin No. Signal I/O Pin No. Signal I/O Pin No. Signal I/O Pin No. Signal I/O
1GND 1 GND 1 EP13I/O 1 EP12I/O
2 GND 2 GND 2 ED0I/O 2 EP11I/O
3 GND 3 GND 3 ED1I/O 3 EP10I/O
4 GND 4 GND 4 ED2I/O 4 EP03I/O
5 GND 5 GND 5 ED3I/O 5 EP02I/O
6 GND 6 GND 6 ED4I/O 6 EP01I/O
7 GND 7 GND 7 ED5I/O 7 EP00I/O
8 GND 8 GND 8 D 6 /CNTR0 I/O 8 P43/AIN7 I/O
9 GND 9 GND 9 D 7 /CNTR1 I/O 9 P42/AIN6 I/O
10 GND 10 GND 10 P50I/O 10 P41/AIN5 I/O
11 GND 11 GND 11 P51I/O 11 P40/AIN4 I/O
12 GND 12 GND 12 P52I/O 12 A IN3 /COM1+ I
13 GND 13 GND 13 P53I/O 13 A IN2 /COM1- I
14 GND 14 GND 14 P20/SCK I/O 14 A IN1 /COM0+ I
15 GND 15 GND 15 P21/SOUT I/O 15 A IN0 /COM0- I
16 GND 16 GND 16 P22/SIN I16P33I/O
17 GND 17 GND 17 RESET I 17 P32I/O
18 GND 18 GND 18 CNVSS -18P31/INT1 I/O
19 GND 19 GND 19 XOUT -19P30/INT0 I/O
20 GND 20 GND 20 XIN -20VDCE I
21 GND 21 GND 21 VSS 21 VDD
22 GND 22 GND 22 NC - 22 NC -
23 GND 23 GND 23 NC - 23 NC -
24 GND 24 GND 24 NC - 24 NC -
25 GND 25 GND 25 NC - 25 NC -