Rev. 4.00 Sep. 14, 2005 Page xlv of l
Table 7.8 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 1)...............186
Section 8 X/Y Memory
Table 8.1 X/Y Memory Specifications................................................................................. 193
Section 9 Exception Handling
Table 9.1 Exception Event Vectors.......................................................................................204
Table 9.2 Type of Reset........................................................................................................206
Table 9.3 Instruction Positions and Restriction Types..........................................................210
Table 9.4 SPC Value When a Re-Execution Type Exception Occurs in Repeat Control.....213
Table 9.5 Exception Acceptance in the Repeat Loop........................................................... 214
Table 9.6 Instruction Where a Specific Exception Occurs
When a Memory Access Exception Occurs in Repeat Control.............................215
Section 10 Interrupt Controller (INTC)
Table 10.1 Pin Configuration..................................................................................................221
Table 10.2 Interrupt Sources and IPRB to IPRJ..................................................................... 224
Table 10.3 Correspondence between Interrupt Sources and IMR0 to IMR10........................230
Table 10.4 Correspondence between Interrupt Sources and IMCR0 to IMCR10...................232
Table 10.5 Interrupt Exception Handling Sources and Priority..............................................236
Section 11 User Break Controller (UBC)
Table 11.1 Specifying Break Address Register...................................................................... 246
Table 11.2 Specifying Break Data Register............................................................................248
Table 11.3 Data Access Cycle Addresses and Operand Size Comparison Conditions...........258
Section 12 Bus State Controller (BSC)
Table 12.1 Pin Configuration..................................................................................................272
Table 12.2 Address Space Map 1 (CMNCR.MAP = 0)..........................................................275
Table 12.3 Address Space Map 2 (CMNCR.MAP = 1)..........................................................276
Table 12.4 Correspondence between External Pin MD3 and Bus Width of Area 0...............277
Table 12.5 32-Bit External Device Access and Data Alignment............................................321
Table 12.6 16-Bit External Device Access and Data Alignment............................................322
Table 12.7 8-Bit External Device Access and Data Alignment..............................................323
Table 12.8 Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (1)-1............................................................................340
Table 12.8 Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (1)-2............................................................................341
Table 12.9 Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (2)-1............................................................................342
Table 12.9 Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (2)-2............................................................................343