Rev. 4.00 Sep. 14, 2005 Page xliv of l
Table 2.31 DSP Operation Instructions.................................................................................... 90
Table 2.32 DC Bit Update Definitions..................................................................................... 96
Table 2.33 Examples of NOPX and NOPY Instruction Codes.................................................98
Section 3 DSP Operation
Table 3.1 Variation of ALU Fixed-Point Operations............................................................100
Table 3.2 Correspondence between Operands and Registers............................................... 100
Table 3.3 Variation of ALU Integer Operations...................................................................104
Table 3.4 Variation of ALU Logical Operations.................................................................. 106
Table 3.5 Variation of Fixed-Point Multiply Operation....................................................... 108
Table 3.6 Correspondence between Operands and Registers............................................... 108
Table 3.7 Variation of Shift Operations................................................................................109
Table 3.8 Operation Definition of PDMSB.......................................................................... 114
Table 3.9 Variation of PDMSB Operation............................................................................115
Table 3.10 Variation of Rounding Operation......................................................................... 116
Table 3.11 Definition of Overflow Protection for Fixed-Point Arithmetic Operations..........117
Table 3.12 Definition of Overflow Protection for Integer Arithmetic Operations..................117
Table 3.13 Variation of Local Data Move Operations............................................................122
Table 3.14 Correspondence between Operands and Registers............................................... 123
Table 3.15 Address Value to be Stored into SPC (1)..............................................................125
Table 3.16 Address Value to be Stored into SPC (2)..............................................................126
Table 3.17 RS and RE Setting Rule........................................................................................128
Table 3.18 Summary of DSP Data Transfer Instructions....................................................... 133
Section 4 Clock Pulse Generator (CPG)
Table 4.1 Pin Configuration and Functions of the Clock Pulse Generator...........................146
Table 4.2 Clock Operating Modes........................................................................................146
Table 4.3 Relationship between Clock Mode and Frequency Range....................................147
Section 6 Power-Down Modes
Table 6.1 States of Power-Down Modes.............................................................................. 164
Table 6.2 Pin Configuration..................................................................................................165
Table 6.3 Register States in Standby Mode..........................................................................172
Section 7 Cache
Table 7.1 Cache Specifications.............................................................................................179
Table 7.2 Address Space Subdivisions and Cache Operation...............................................179
Table 7.3 LRU and Way Replacement................................................................................. 181
Table 7.4 Way to be Replaced when a Cache Miss Occurs in PREF Instruction.................185
Table 7.5 Way to be Replaced when a Cache Miss Occurs in Other than PREF Instruction.. 185
Table 7.6 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 0)...............185
Table 7.7 LRU and Way Replacement (when W2LOCK = 0 and W3LOCK = 1)...............186