Rev. 4.00 Sep. 14, 2005 Page xlii of l
Figure 25.48 MTU Clock Input Timing..................................................................................... 956
Figure 25.49 POE Input/Output Timing.....................................................................................957
Figure 25.50 I2C Bus Interface Input/Output Timing.................................................................959
Figure 25.51 TCK Input Timing.................................................................................................960
Figure 25.52 TRST Input Timing (Reset-Hold State)................................................................ 961
Figure 25.53 H-UDI Data Transfer Timing................................................................................961
Figure 25.54 Boundary-Scan Input/Output Timing....................................................................961
Figure 25.55 USB Clock Timing................................................................................................962
Figure 25.56 Output Load Circuit..............................................................................................964
Appendix
Figure C.1 Package Dimensions.................................................................................................973