Rev. 5.00, 09/03, page 96 of 760
• TLB invalid exception
Conditions: Comparison of TLB addresses shows address match but the TLB entry valid
bit (V) is 0.
Operations: The virtual address (32 bits) that caused the exception is set in TEA and the
cor resp onding vi rtua l page numbe r (22 bit s) is set i n PTEH (31–10). Th e AS ID o f PT E H
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bits in MMUCR.
PC and SR of the instruction that generated the e xception are saved to SP C and SSR,
respectively. If the exception occurr e d during a re ad, H'040 is set in EXPEVT; if the exception
occurred during a write, H'060 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0100.
• Initial page write exceptio n
Conditions: A hit occurred to the TLB for a store access, but the TLB entry data bit (D) is
0.
This occurs for initial wri tes to the page regist ered by the load.
Operations: The virtual address (32 bits) that caused the exception is set in TEA and the
cor resp onding vi rtua l page numbe r (22 bit s) is set i n PTEH (31–10). Th e AS ID o f PT E H
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bit in MMUCR.
PC and SR of the instruction that generated the e xception are saved to SP C and SSR,
respectively. H'080 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a
branch occu rs to PC = VBR + H'0100.
• TLB protection exception
Conditions: When a hit access violates the TLB protection information (PR bits) shown
below:
PR Privileged mode User mode
00 Only read enabled No access
01 Read/write enabled No access
10 Only read enabl ed Only read enabl ed
11 Read/write enabled Read/write enabled
Operations: The virtual address (32 bits) that caused the exception is set in TEA and the
cor resp onding vi rtua l page numbe r (22 bit s) is set i n PTEH (31–10). Th e AS ID o f PT E H
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bits in MMUCR.
PC and SR of the instruction that generated the e xception are saved to SP C and SSR,
respectively. If the exception occurre d during a read, H'0A0 is set in EXPEVT; if the exception
occurred during a write, H'0C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0100.