Rev. 5.00, 09/03, page 98 of 760
• Illegal slot instruction
Conditions:
a. When undefine d code in a delay sl ot is decoded
Delay br a nch instructions: JMP, J S R, BRA, BRAF, BSR, B SRF, RTS, RTE, BT/S,
BF/S
b. When an instru ct i on t hat rewri t es PC in a delay slot i s decoded
Instruc tions that rewrite PC: JMP, JSR, B RA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR
c. When a priv i l eged ins t ruction in a delay slot is decoded in user mode
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; Instructions that access
GBR with LDC/STC are not privileged instructions and therefore do not app ly.
Operations: PC of the immediately precedin g delay branch instruction is saved to SPC. SR
of the instruction that generated the exception is saved to SSR. H'1A0 is set in EXPEVT.
The BL, MD, and RB b its in SR are set to 1 and a branch occurs to PC = VBR + H'0100.
When an undefined instru ction ot her than H'Fxxx is decoded, operat i on cannot be
guaranteed.
• User break point trap
Conditions: When a break condition set in the user break controller is satisfied
Operations: When a post-execu tion break occurs, PC of the instruction immediately after
the instruction that set the break point is set in SPC. If a pre-execution break occurs, PC of
the instruction that set the break point is set in SPC. SR when the break occurs is set in
SSR. H'1E0 is set in EX PEVT. The BL, MD, and RB bits in SR are set to 1 and a branch
occurs to PC = VBR + H'0100. See section 7, User Break Controller, for more information.
• DMA address error
Conditions:
a. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
b. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
4n + 3)
Operations: PC of the instruction immediately after the instruction executed before the
exception occurs is saved to SPC. SR when the exception occurs is saved to SSR. H'5C0 is
set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC =
VBR + H'0100.