Rev. 5.00, 09/03, page 117 of 760
Section 6 Interrupt Controller (INTC)
6.1 Overview
The interrupt controller (INTC) asc ertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the o rder of priority of each interrupt, allowing the
user to process interrupt requests according to the user-set priority.
6.1.1 Features
The INTC has the following features:
• 16 levels of interrupt prior ity can be set: By setting the five interrupt-priority registers, the
priorities of on-chip peripheral module, IRQ, and PINT interrupts can be selected fr om 16
levels for individual request sources.
• NMI noise canceler function: An NMI input-level bit indicates the NMI pin state. By reading
this bit in the interrupt exception service routine, the pin state can be checked, enabling it to be
used as a noise canceler.
• External devices can be notified that an interrupt has been received (IRQOUT): When the
SH7709S has released the bus, the external bus master can be notified that an external
interrupt, an on-chip peripheral module interrupt, or a memory refresh request has occurred,
enabling the bus to be requested.