Rev. 5.00, 09/03, page 237 of 760
Bits 10 and 9—Area 0 Burst ROM Control (A0BST1, A0BST0): Specify whether to use burst
ROM in physical space area 0. When burst ROM is used, these bits set the number of burst
transfers.
Bit 10: A0BST1 Bit 9: A0BST0 Description
0 0 Access area 0 access ed as ordin ary me mory
(Initial value)
1 Access area 0 access ed as burst R OM (4 consecutive
accesses). Can be used when bus width is 8, 16, or 32.
1 0 Access area 0 access ed as burst R O M (8 consecutive
accesses). Can be used when bus width is 8 or 16.
Should not be spe cif ied w hen bus width is 16 or 32.
1 Access area 0 access ed as burst R OM (16 consecutive
accesses) . Can be used only when bus width is 8.
Should not be spe cif ied w hen bus width is 16 or 32.
Bits 8 and 7—Area 5 Burst Enable (A5BST1, A5BST0): Specify whether to use burst ROM
and PCMCI A burst mod e in physical space area 5. When burst ROM and PCMC IA burst mod e
are used, these bits set the number of burst transfers.
Bit 8: A5BST1 Bit 7: A5BST0 Description
0 0 Access area 5 access ed as ordin ary me mory
(Initial value)
1 Burst access of area 5 (4 consecutive accesses). Can
be used when bus width is 8, 16, or 32.
1 0 Burst access of area 5 (8 consecutive accesses). Can
be used when bus width is 8 or 16. Should not be
specified when bus width is 32.
1 Burst access of area 5 (16 consecutive accesses). Can
be used only when bus width is 8. Should not be
specified when bus width is 16 or 32.
Bits 6 and 5—Area 6 Burst Enable (A6BST1, A6BST0): Specify whether to use burst ROM
and PCMCI A burst mod e in physical space area 6. When burst ROM and PCMC IA burst mod e
are used, these bits set the number of burst transfers.