Rev. 5.00, 09/03, page 238 of 760
Bit 6: A6BST1 Bit 5: A6BST0 Description
0 0 Access area 6 access ed as ordin ary me mory
(initial value)
1 Burst access of area 6 (4 consecutive accesses). Can
be used when bus width is 8, 16, or 32.
1 0 Burst access of area 6 (8 consecutive accesses). Can
be used when bus width is 8 or 16. Should not be
specified when bus width is 32.
1 Burst access of area 6 (16 consecutive accesses). Can
be used only when bus width is 8. Should not be
specified when bus width is 16 or 32.
Bits 4 t o 2—Area 2 , Are a 3 Memory Type (DRAMTP2, DRAMT P1, D RAMTP0 ) : Designate
the types of memory connected to physical space areas 2 an d 3. Ordinary me mory, such as ROM,
SRAM, or flash ROM, can be directly connected. Synchronous DRAM can also be directly
connected.
Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description
000Areas 2 and 3 are ordinary memory
(Initial value)
1 Reserved (Setting prohibited)
1 0 Area 2: ordinary memory; area 3:
synchronous DRAM*2
1 Areas 2 and 3 are synchronous DRAM*1
*2
100Reserved (Setting prohibited)
1 Reserved (Setting prohibited)
1 0 Reserved (Setting prohibited)
1 Reserved (Setting prohibited)
Notes: 1. When sel ecting this mode, set the sa me bus width for ar ea 2 and are a 3.
2. Do not access synchronous DRAM when clock ratio Iφ:Bφ = 1:1
Bit 1—Area 5 Bus Type (A5PCM): Designates whether to access physical space area 5 as
PCMCIA space.
Bit 1: A5PCM Description
0 Physical spac e area 5 ac cessed as ord inary m emory (Initial value)
1 Physica l space area 5 ac ces sed as PCMCIA space