Renesas SH7709S - page 294

Rev. 5.00, 09/03, page 250 of 760
Bits 11 , 7, and 6—Area 5 Address O
OO
OE
EE
E/W
WW
WE
EE
E Assert Delay (A5TED2, A5TED1, A5TED0 ):
Specify the delay time from address output to OE/WE assertion for the PCMCIA interface
connected to area 5.
Bit 11:
A5TED2 Bit 7: A5TED1 Bit 6: A5TED0 Description
0000.5-cycle delay (Initial value)
1 1.5-cycle de lay
102.5-cycle delay
1 3.5-cycle de lay
1004.5-cycle delay
1 5.5-cycle de lay
106.5-cycle delay
1 7.5-cycle de lay
Bits 10 , 5, and 4—Area 6 Address O
OO
OE
EE
E/W
WW
WE
EE
E Assert Delay (A6TED2, A6TED1, A6TED0 ): The
A6TED bits specify the delay time from address output to OE/WE assertion for the PCMCIA
interface connected to area 6.
Bit 10:
A6TED2 Bit 5: A6TED1 Bit 4: A6TED0 Description
0000.5-cycle delay (Initial value)
1 1.5-cycle de lay
102.5-cycle delay
1 3.5-cycle de lay
1004.5-cycle delay
1 5.5-cycle de lay
106.5-cycle delay
1 7.5-cycle de lay