Rev. 5.00, 09/03, page 260 of 760
10.3 BSC Operation
10.3.1 Endian/Access Size and Data Alignment
The SH7709S su pport s both big endian, in which the 0 address is the most significant byte in the
byte data, and little endian, in which the 0 address is the least sig ni ficant byte. Switching between
the two is designated by an external pin (MD5 pin) at the time of a power-on reset. After a power-
on reset , big endian i s engaged wh en MD 5 is l ow; li t tle endian is engaged wh en MD5 is hig h.
Three data bus widths are available for ordinary memory (byte, word, longword) and two data bus
widths (word and longword) for synchronous DRAM. For the PCMCIA interface, choose from
byte and word . This means da t a alignmen t is done by match ing the devi ce’s data wid th and
endian. The access unit must also be matched to the device’ s bus width. This also means that when
longword data is read from a byte-width device, four read operations must be p erformed. In the
SH7709S, data alignment and conversion of data length is performed automatically between the
respective interfaces.
Tables 10.7 to 10. 12 show the relationshi p betw een endian, de vice data width, and access unit.
Table 10.7 32-Bit External Device/Big-Endian A ccess and Data Alignment
Data Bus Strobe Signals
Operation D31–D24 D23–D16 D15–D8 D7–D0
W
WW
WE
EE
E3
33
3,
DQMUU
W
WW
WE
EE
E2
22
2,
DQMUL
W
WW
WE
EE
E1
11
1,
DQMLU
W
WW
WE
EE
E0
00
0,
DQMLL
Byte access
at 0 Data
7–0 — ——Asserted
Byte access
at 1 —Data
7–0 —— Asserted
Byte access
at 2
——Data
7–0
—Asserted
Byte access
at 3
———Data
7–0
Asserted
Word acces s
at 0
Data
15–8
Data
7–0
— — Asserted Asserted
Word acces s
at 2 ——Data
15–8 Data
7–0 Asserted Asserted
Longword
acce ss at 0
Data
31–24
Data
23–16
Data
15–8
Data
7–0
Asserted Asserted Asserted Asserted