Rev. 5.00, 09/03, page 279 of 760
Table 10.13 Relationship between Bus Width, AMX Bits, and Address Multiplex Output
Setting External Address Pins
Bus
Width Memory
Type AMX
3AMX
2AMX
1AMX
0Output
Timing A1 t o
A8 A9 A10 A11 A12 A13 A14 A15 A16
32 bits 4M ×
16bits ×
4banks*1
1101Column
address
A1 to
A8
A9 A10 A11 L/H*3A13 A23 A24*4A25*4
Row
address A10 to
A17 A18 A19 A20 A21 A22 A23 A24*4A25*4
2M ×
16bits ×
4banks*2
0101Column
address
A1 to
A8
A9 A10 A11 L/H*3A13 A23*4A24*4
Row
address
A10 to
A17
A18 A19 A20 A21 A22 A23*4A24*4
1M ×
16bits ×
4banks*2
0100Column
address A1 to
A8 A9 A10 A11 L/H*3A13 A22*4A23*4
Row
address
A9 to
A16
A17 A18 A19 A20 A21 A22*4A23*4
2M ×
8bits ×
4banks*2
0101Column
address A1 to
A8 A9 A10 A11 L/H*3A13 A23*4A24*4
Row
address
A10 to
A17
A18 A19 A20 A21 A22 A23*4A24*4
512k ×
32bits ×
4banks*2
0111Column
address
A1 to
A8
A9 A10 A11 L/H*3A21*4A22*4A15
Row
address
A9 to
A16
A17 A18 A19 A20 A21*4A22*4A23
16 bits 8M ×
16bits ×
4banks*1
1110Column
address
A1 to
A8
A9 A10 L/H*3A12 A23 A24*4A25*4
Row
address A11 to
A18 A19 A20 A21 A22 A23 A24*4A25*4
4M ×
16bits ×
4banks*2
1101Column
address
A1 to
A8
A9 A10 L/H*3A12 A22 A23*4A24*4
Row
address A10 to
A17 A18 A19 A20 A21 A22 A23*4A24*4