Rev. 5.00, 09/03, page 280 of 760
Setting External Address Pins
Bus
Width Memory
Type AMX
3AMX
2AMX
1AMX
0Output
Timing A1 to
A8 A9 A10 A11 A12 A13 A14 A15 A16
2M ×
16bits ×
4banks*2
0101Column
address
A1 to
A8
A9 A10 L/H*3A12 A22*4A23*4A24
Row
address A10 to
A17 A18 A19 A20 A21 A22*4A23*4A24
1M ×
16bits ×
4banks*2
0100Column
address
A1 to
A8
A9 A10 L/H*3A12 A21*4A22*4A15
Row
address
A 9 to
A16
A17 A18 A19 A20 A21*4A22*4A23
2M ×
8bits ×
4banks*2
0101Column
address A1 to
A8 A9 A10 L/H*3A12 A22*4A23*4A24
Row
address
A10 to
A17
A18 A19 A20 A21 A22*4A23*4A24
Notes: 1. Only RAL3L or CASL is output.
2. When addresses are upper 32 Mbytes, RAS3U or CASU is output.
When addresses are low er 32 Mbyt es, RAS3L or CASL is output.
3. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
4. Bank address specification