Rev. 5.00, 09/03, page 286 of 760
CKIO
CSn
RD/WR
RAS3x
CASx
DQMxx
D31 to D0
(read)
BS
Tr Tc1 Tc2 Tc3 Tc4 (Trwl) (Tpc)
A
ddress
upper bits
A
12, A11,
A
10 or A9
A
ddress
lower bits
Figure 10.17 Basic Timing for Synchronous DR AM Burst Write