Rev. 5.00, 09/03, page 288 of 760
CKIO
CSn
RD/WR
RAS3x
CASx
DQMxx
D31 to D0
BS
A
ddress
upper bits
A
12 or A10
A
ddress
lower bits
CKE
Tr Tc1 (Trwl) (Tpc)
Figure 10. 18 Basic Timing for Synchronous DRAM Single Write