Rev. 5.00, 09/03, page 303 of 760
Before mode register setting, a 100 µs idle time (depending on the memory manufacturer) must be
guarant eed aft e r powe ring on requeste d by the synch ron ous DRAM. If the reset signal pu l s e width
is greater than this idle time, there is no problem in performing mode register setting immediately.
The number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must
be executed. This is usually achieved automatically w h ile various kinds of initialization are being
performed after auto-refresh s etti ng , but a way of carrying this ou t more dependably is to set a
short refresh requ es t generation interval just while these dummy cycles are being ex ecuted. With
simple read or write access, the address counter in the syn chronous DRAM used for auto-
refresh ing i s not initialized, and so the cycle must always be an auto-refre sh cycle.
CKIO
A11
A12 or A10
A9 to A2
CSn
RD/WR
RAS3U or RAS3L
CASU or CASL
D31 to D0
CKE
TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4
(High)
A
15 to A13
or A15 to A12
Figure 10.28 Synchronous DRAM Mode Write Timing