Rev. 5.00, 09/03, page 305 of 760
T1TWTWTB2 TB1 TWTB2
CKIO
A
25 to A4
A
3 to A0
CSn
RD/WR
RD
D31 to
D0
BS
WAIT
T2
Note: For a write cycle, a basic bus cycle (write cycle) is performed.
TB1
Figure 10.29 Burst ROM Wait Access Timing