Rev. 5.00, 09/03, page 319 of 760
10.3.7 Waits between Access Cycles
A problem associated with higher external memor y bus operating frequencies is that data buffer
turn-off on completion of a read from a low-speed device may be t oo slow, causing a collision
with data in th e nex t access . This results in lower reliability or incorrect operation. To avoid this
problem, a data collision prevention feature has been provided. This memorizes the preceding
access area and the kind of read/write. If there is a possibility of a bus collision when the next
access is started, a wait cycle is inserted before the access cycle thus preventing a data collision.
There are two cases in which a wait cycle is inserted: when an access is followed by an access to a
different area, and when a read access is followed by a write ac cess from the SH7709S. When the
SH7709S performs consecutive write cycles, the data transfer direction is fixed (from the
SH7709S to other memory) and there is no problem. With read accesses to the same area, in
principle, data is output from the same data buffer, and wait c ycle in sertion is not performed. Bits
AnIW1 and AnIW0 (n = 0, 2–6) in WCR1 specify the number of idle cycles to be inserted
betw een access cycles when a physi cal space area access i s followed by an access to another a r ea,
or when the SH7709S performs a write access after a read access to physical space area n. If there
is originally space between accesses, the number of idle cy cles inse rted is the specified number of
idle cycles minus the number of empty cycles.
Waits are not inse rted between accesses when bus arb itration is p er formed, since empty cycles are
inserted for arbitratio n purposes.