Rev. 5.00, 09/03, page 320 of 760
T1
CKIO
CSm
CSn
A
25 to A0
BS
RD/WR
RD
D31 to D0
T2Twait T1T2Twait T1T2
Area m read
Area m inter-access wait specification Area n inter-access wait specification
Area n space read Area n space write
Figure 10.40 Waits between Access Cycles
10.3.8 Bus Arb i tration
When a bus release request (BREQ) is asserted from an external device, buses are released after
the bus cycle being executed is completed and a bus grant sign al (BACK) is output. The bus is not
released du ring burst transfers f o r cache f ills or write-back , or TAS instruction execution between
the read cycle and write cycle. Bus arbitration is not executed in multiple bus cycles that are
genera ted wh en the data bu s width i s shor ter th an the access size; i.e. in the bus cycles when
longword access is executed f or the 8-bit memory. At the n egation of BREQ, BACK is negated
and bus use is restar ted . See Appendix A.1, Pin States, for the pin states when the bus is released.
The SH7709S sometimes needs to retrieve a bus it has released. For example, when memo ry
generates a refresh request or an interrupt request internally, the SH7709S must perform the
appropriate processing. The SH7709S has a bus request signal (IRQOUT) for this purpose. When
it must retrieve the bus, it asserts the IRQOUT signal. Devices asserting an external bus release
request receive the assertion of the IRQOUT signal and negate the BREQ signal to release the bus.
The SH7709S retri e ves the bus and carries ou t th e proces sing.