
Rev. 5.00, 09/03, page 331 of 760
11.1.4 Register Configuration
Table 11.2 summarizes the DMAC registers. The DMAC has a total of 17 registers: each channel
has four registers, and one overall DMAC control register.
Table 11.2 DMAC Registers
Channel Name Abbrevi-
ation R/W Initial Value Address Register
Size Access
Size
0 DMA source address
register 0
SAR0 R/W Undefined H'04000020
(H'A4000020)*432 16, 32*2
DMA destination
address regist er 0
DAR0 R/W Undefined H'04000024
(H'A4000024)*432 16, 32*2
DMA transfer count
register 0 DMATCR0 R/W Undefined H'04000028
(H'A4000028)*424 16, 32*3
DMA channel control
register 0 CHCR0 R/W*1H'00000000 H'0400002C
(H'A400002C)*432 8, 16, 32*2
1 DMA source address
register 1
SAR1 R/W Undefined H'04000030
(H'A4000030)*432 16, 32*2
DMA destination
address regist er 1
DAR1 R/W Undefined H'04000034
(H'A4000034)*432 16, 32*2
DMA transfer count
register 1 DMATCR1 R/W Undefined H'04000038
(H'A4000038)*424 16, 32*3
DMA channel control
register 1 CHCR1 R/W*1H'00000000 H'0400003C
(H'A400003C)*432 8, 16, 32*2
2 DMA source address
register 2
SAR2 R/W Undefined H'04000040
(H'A4000040)*432 16, 32*2
DMA destination
address regist er 2
DAR2 R/W Undefined H'04000044
(H'A4000044)*432 16, 32*2
DMA transfer count
register 2 DMATCR2 R/W Undefined H'04000048
(H'A4000048)*424 16, 32*3
DMA channel control
register 2 CHCR2 R/W*1H'00000000 H'0400004C
(H'A400004C)*432 8, 16, 32*2