Rev. 5.00, 09/03, page 336 of 760
11.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
DMA channel control registers 0–3 (CHCR0–CHCR3) are 32-bit readable/writable registers that
specify the operation mode, transfer method, etc., for each channel.
Bit 20 is only used in CHCR3; it is not us ed in CHCR0 to CHCR2. Consequently, writing t o this
bit is invalid in CHCR0 to CHCR2; 0 is read if this bit is read. Bit 19 is only used in CHCR2; it is
not used in CHCR0, CHCR1, and CHCR3 . Consequently, writing to this bit is invalid in CHCR0,
CHCR1, and CHCR3; 0 is read if this bit is read. Bits 6 and 16 to 18 are only used in CHCR0 and
CHCR1; th ey are not used in CHCR2 and CHCR3. Cons equently, writing to these bits is invalid
in CHCR2 and CHCR3; 0s are read if these bits are read.
These register values are i nitia liz ed to 0 in a r eset. The previous value is retained in standby mode.
Bit: 31 ... 21 20 19 18 17 16
— ... — DI RO RL AM AL
Initial value:0...000000
R/W: R ... R (R/W)*2(R/W)*2(R/W)*2(R/W)*2(R/W)*2
Bit: 15 14 13 12 11 10 9 8
DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit:76543210
—DSTMTS1TS0IETEDE
Initial value:00000000
R/W: R (R/W)*2R/W R/W R/W R/W R/(W)*1R/W
Notes: 1. Only 0 can be written to the TE bit after 1 is read.
2. The DI, RO, RL, AM, AL, and DS bits are not included in some channels.