Rev. 5.00, 09/03, page 338 of 760
Bit 17—Acknowledge Mode Bit (AM): Specifies whether DACK is output in the data read cycle
or in the data write cycle in dual address mode.
DACK is always output in single address mode, regardless of this bit specification.
This bit is only val i d in CHCR0 and CHCR1. W riting to this bit is invalid in CHCR2 a n d
CHCR3; 0 is read if this bit is r ead. The write value shou ld always be 0.
Bit 17: AM Description
0 DACK output in read cycle (Initial value)
1 DACK output in write cycle
Bit 16—Acknowledge Level (AL): Speci fies whe ther DACK (acknowledge) signal output is
active-high or active-low.
This bit is only val i d in CHCR0 and CHCR1. W riting to this bit is invalid in CHCR2 a n d
CHCR3; 0 is read if this bit is r ead. The write value shou ld always be 0.
Bit 16: AL Description
0 Active-low DACK output (Initial value)
1 Active-high DACK output
Bits 15 and 14—Destination Address Mode Bits 1 and 0 (DM1, DM0): Select whether the
DMA destination address is incremented, decremented, or left fixed.
Bit 15: DM1 Bit 14: DM0 Description
0 0 Fixed destination address (Initial value)
0 1 Destination address is incremented (+1 in 8-bit transfer, +2 in
16-bit transfer, +4 in 32-bit tran sfer, +16 in 16-by te tran sfer)
1 0 Destinatio n address is decr eme nted (–1 in 8-bit transfer, –2 i n
16-bit transfer, –4 in 32-bit tran sfer; illegal setti ng in 16-by te
transfer)
1 1 Setting pro hibi ted