Rev. 5.00, 09/03, page 370 of 760
CKIO
DRAK
DREQ
DACK
Bus cycle DMAC(R)
DMAC(W)DMAC(R)
DMAC(W)
DMAC(R)
CPU
1st sampling 2nd sampling 3rd sampling
Figure 11.20 Burst Mode, Level Input