Renesas SH7709S - page 442

Rev. 5.00, 09/03, page 398 of 760
Because the internal bus for the SH7709S on-chip peripheral modules is 16 bits wide, a time lag
can occur between the time when the upper 16 bits and lower 16 bits are read. Since TCNT counts
sequentially, this time lag can create discrepancies betwee n the data in the upper and lower halves.
To correct the discrepancy, a buffer register is connected to TCNT so that the upper and lower
halves are not read separately. The entire 32-bit data in TCNT can thus be read at once.
TCNT is initialized to H'FFFFFFFF by a power-on reset or manual reset, but is not initialized, and
retains its contents, in standby mode.
Bit: 31 30 29 28 27 26 25 24
Initial value:11111111
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23 22 21 20 19 18 17 16
Initial value:11111111
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8
Initial value:11111111
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit:76543210
Initial value:11111111
R/W: R/W R/W R/W R/W R/W R/W R/W R/W