Rev. 5.00, 09/03, page 400 of 760
12.3 TMU Operation
Each of three channels has a 32-bit timer counter (TCNT) and a 32-bit timer constant register
(TCOR). TCNT counts down. The auto-reload function enables cycle counting and counting by
external events. Channel 2 has an input capture function.
12.3.1 General Operation
When the STR0–STR2 bits in the timer start register (TSTR) are set to 1, the corresponding timer
counter (T CNT) starts c ounting. When a TCNT underflows , the UNF flag of the corresponding
timer control register (TCR) is set. At this time, if the UNIE bit in TCR is 1, an interrupt request is
sent to the CPU. Al so at this time, the value is copied from TCOR to TCNT and the dow n-count
operation is continued.
The count operation is set as fo llows (figure 12.2):
1. Select the counter clock with the TPSC2–TPSC0 bits in the timer control register (TCR). If the
external clock is selected, set the TCLK pin to input mode with the TOCE bit in TOCR, and
select its edge with the CKEG1 and CKEG0 bits in TCR.
2. Use the UNIE bit in TCR to set whether to ge nerate an interrupt when TCN T underflows.
3. When using the input capture function, set the ICPE bits in TCR, including the choice of
whether or not to use the inte rrupt func tion (chann e l 2 only) .
4. Set a value in the timer constant register (TCOR) (the cycle is the set value plus 1).
5. Set the initial value in the timer counter (TCNT).
6. Set the STR bit in the timer start register (TSTR) to 1 to start operation.