Rev. 5.00, 09/03, page 440 of 760
14.2.7 Serial Status Register (SCSSR)
The serial status register (SCSSR) is an 8-bit register containing multiprocessor bit values, and
status flags th at indicate the SCI operating state.
The CPU can always read and write to SCSSR, but cannot write 1 to the status flags (TDRE,
RDRF, ORER, PE R, and FER). These flags ca n be cleared to 0 only if they have first been read
(after being set to 1). Bit s 2 (TEND) and 1 (MPB) are read-only bits that cannot be written.
SCSSR is initialized to H'84 by a reset and in standby or module standby mode.
Bit:76543210
TDRE RDRF ORER FER PER TEND MPB MPBT
Initial value:10000100
R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*RRR/W
Note: * The only value that can be written is 0 to clear the flag.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from SCTDR into SCTSR and new serial transmit data can be written in SCTDR.
Bit 7: TDRE Description
0 SCTD R contains val id transmit data
[Clearing condition]
TDRE is cleared to 0 when software reads TDRE after it has been set to 1.
1 SCTDR does not contain valid transmit data (Initial value)
[Setting conditions]
(1) TDRE is set to 1 when the chip is reset or enters standby mode.
(2) The TE bit in the serial control register (SCSCR) is cleared to 0.
(3) SCTD R contents are load ed into SCTSR , so new data can be written in
SCTDR.