Rev. 5.00, 09/03, page 560 of 760
17.1.4 Register Configuration
The IrDA has the internal registers shown in table 17.2. These registers select IrDA or SCIF
mode, specify the data format and a bit rate, and control the transmit and receive units.
Table 17.2 IrDA Registers
Register Name Abbreviation R/W Initial Value Address Access
Size
Serial mode register 1 SCSMR1 R/ W H'00 H'04000140
(H'A4000140)*28 bits
Bit rate register 1 SCBRR1 R/W H'FF H'04000142
(H'A4000142)*28 bits
Serial control register 1 SCSCR1 R/ W H'00 H'040001 44
(H'A4000144)*28 bits
Transmit FIFO data register 1 SCFTDR1 W — H'04000146
(H'A4000146)*28 bits
Serial status register 1 SCSSR1 R/( W)*1H'0060 H'04000148
(H'A4000148)*216 bits
Receive FIFO data register 1 SCFRDR1 R Undefined H'0400014A
(H'A400014A)*28 bits
FIFO control register 1 SCFCR1 R/W H'00 H'0400014C
(H'A400014C)*28 bits
FIFO data count regi ster 1 SCFDR1 R H'0000 H'0400014E
(H'A400014E)*216 bits
Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on,
either access these registers from the P2 area of logical space or else make an appropriate
setting using the MMU so that these registers are not cached.
1. Only 0 can be written to clear the flag.
2. When address tran slation by the MM U does not apply , the address in parentheses
should be used.